Embedded opcode within an intermediate value passed between instructions

[0045]FIG. 1 schematically illustrates a data processing system 2 including a graphics processing unit 4 coupled to a memory 6. The memory 6 stores program instructions to be executed and data values, such as graphics data values, to be manipulated. The graphics processing unit 4 includes fetch circuitry 8 for fetching program instructions from the memory 6. Instruction decoder circuitry 10 decodes the fetched program instructions and generates control signals for controlling data processing circuitry 12 to perform desired data processing operations. The data processing circuitry 12 may include a plurality of execution pipelines, such as arithmetic pipeline, a SIMD pipeline, a floating point pipeline etc.

[0046]In the context of a graphics processing unit 4 when processing throughput may be more significant than latency, it is known to provide processing pipelines which are deep and are arranged such that they do not stall when executing a sequence of program instructions to evaluate a