Circuit for transistor level implementation scheme of five input end combination logical circuit

The invention discloses a circuit for a transistor level implementation scheme of a five input end combination logical circuit. The circuit comprises a first triode, a second triode, a third triode, a fourth triode, a fifth triode, a sixth triode, a seventh triode and the like, a grid electrode of the first triode is connected with a grid electrode of the sixth triode, a source electrode of the first triode is connected with a drain electrode of the second triode, a grid electrode of the second triode is connected with a grid electrode of the seventh triode, a source electrode of the second triode is connected with a drain electrode of the third triode, a grid electrode of the third triode is connected with a grid electrode of an eighth triode, a grid electrode of the fourth triode is connected with a grid electrode of a ninth triode, a source electrode of the fourth triode is connected with a drain electrode of the fifth triode, and a grid electrode of the fifth triode is connected with a grid electrode of a thirteenth triode. Accordingly, the number of transistors is reduced, the purpose of reducing the number of the transistors is achieved, and finally the purpose of greatly reducing the silicon area occupied by the same logical function is achieved.