Circuit for transistor level implementation scheme of five input end combination logical circuit
A combinational logic, five-input technology, applied in logic circuits, logic circuits with logic functions, electrical components, etc., can solve the problems of large transmission delay, large signal transmission delay, large silicon chip area, etc., to reduce the number of transistors, The effect of wafer area reduction
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[0016] Hereinafter, preferred embodiments of the present invention are given in conjunction with the drawings to illustrate the technical solutions of the present invention in detail.
[0017] Such as figure 1 As shown, the circuit of the five-input combinatorial logic of the present invention includes a first transistor Q1, a second transistor Q2, a third transistor Q3, a fourth transistor Q4, a fifth transistor Q5, and a sixth transistor. Transistor Q6, seventh transistor Q7, eighth transistor Q8, ninth transistor Q9, thirteenth transistor Q10, the drain of the first transistor Q1, the drain of the second transistor Q2, The drain of the third transistor Q3, the drain of the fourth transistor Q4 and the drain of the fifth transistor Q5 are connected, the source of the first transistor Q1 and the source of the second transistor Q2 The source of the third transistor Q3, the source of the fourth transistor Q4 and the source of the fifth transistor Q5 are connected, the gate of the f
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