Demultiplexer circuit

Demultiplexer capable of coping with bit deviation of a comma code to suppress increase of operating frequency. The demultiplexer comprises a circuit (20) serially supplied with received data to perform serial-to-parallel conversion on the received data, a comma detection circuit (30) for activating a comma detection signal on detection of coincidence between the serial data transferred on parallel paths with clocks corresponding to received clocks halved in frequency and a comma code, and a control circuit (137-139, 40) for elongating and outputting the activated time duration of the comma detection signal by a predetermined time. The demultiplexer also includes a recovery clock generating circuit (50) composed of a state machine transferred between different states based on the frequency-halved clocks and which, on receipt of an output signal of a control circuit (40), varies the period of the recovery clock to output the resulting clock. The demultiplexer also includes first and second delay circuits (131-133, 134-136) and first and second shift registers (121-125, 126-130) for receiving outputs of the first and second delay circuits to convert outputs into parallel data. The demultiplexer also includes a latch circuit (70) receiving outputs of respective stages of the first and second shift registers in parallel and sampling parallel outputs with recovery clocks to output resulting parallel data. In case of occurrence of bit deviation, recovery clocks are elongated by a predetermined time duration for only one period depending on the state of bit deviation.