Adaptive interface for coupling FPGA modules

a module and interface technology, applied in the direction of logic circuit coupling/interface arrangement, pulse technique, instruments, etc., can solve the problems of high cost, inability to adapt to the i/o wiring of module fpga circuits or model fpga circuits in prototyping systems, etc., to achieve low cost, low latency, and high data rate

Active Publication Date: 2014-11-13
DSPACE DIGITAL SIGNAL PROCESSING & CONTROL ENG
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

The technical effect of this patented technology is that it allows for efficient communication between senders and receivers while maintaining their desired speed and delay times. This means that the process can be done quickly and cheaply without sacrificing quality.

Problems solved by technology

The technical problem addressed in this patent text relates to improving the performance of modular control circuits that use I/O modules due to their low latency and high bandwidth requirements. Conventional methods involve connecting external devices through signal interfaces like pins or solder connections, but these techniques require expensive equipment and long time. Therefore, there is a need for efficient adaptability solutions for modular control circuits without requiring extensive programming effort.

Method used

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  • Adaptive interface for coupling FPGA modules
  • Adaptive interface for coupling FPGA modules
  • Adaptive interface for coupling FPGA modules

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Embodiment Construction

[0049]FIG. 1 shows an FPGA control system 1 according to a preferred embodiment. FPGA control system 1 comprises an FPGA 2 as sender side 3 and a receiver side 4. Receiver side 4 in this exemplary embodiment comprises two I / O modules 5, as is shown in the detail in FIG. 2.

[0050]A serial interface 6 is formed between sender side 3 and receiver side 4. Serial interface 6 is the basis for an adaptive interface 7, which is implemented between FPGA 2 and I / O modules 5 and uses serial interface 6 as the transmission medium. Serial interface 6 is realized as an LVDS interface with a block size of 8 bits for the transmission of data

[0051]A plurality of FPGA applications 8, each of which is connected via register 9 to adaptive interface 7, is implemented in FPGA 2. On receiver side 4 a plurality of hardware implementations 10 is formed in I / O modules 5, which are also connected via register 9 to adaptive interface 7.

[0052]Further, a method for implementing adaptive interface 7 between FPG

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Abstract

A method for implementing an adaptive interface between at least one FPGA with at least one FPGA application and at least one I/O module, which are designed as the corresponding sender side or receiver side, for connection to the FPGA, whereby a serial interface is formed between the at least one FPGA and the at least one I/O module, comprising the steps of configuring a maximum number of registers to be transmitted for each FPGA application, configuring a shared, fixed register width for all registers, setting an enable signal on the sender side for the registers to be transmitted out of the maximum number of registers to be transmitted, transmitting the enable signal from the sender side to the receiver side, and transmitting the registers, for which the enable signal is set, from the sender side to the receiver side.

Description

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Claims

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Application Information

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Owner DSPACE DIGITAL SIGNAL PROCESSING & CONTROL ENG
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