46 results about "Computer architecture" patented technology

Systems and methods for scalable video coding using special inter-layer prediction modes (called telescopic modes) are provided. These modes facilitate accelerated operation of encoders with improved coding efficiency.

The invention relates to a mapping device of a physical communication channel in an orthogonal frequency-division multiplexing system and a mapping method thereof, wherein the method implements the following steps to each flow of symbols which is generated after a code clock in a transmission block is processed, firstly orderly dividing the flow of symbols into a plurality of resource block transmission units with the resource block transmission length, secondly, determining the mapping area which integrates the resource blocks which are corresponding to the flows of symbols and the quality indicated value of the communication channels which are respectively corresponding to the resource blocks in the area, thirdly, mapping the resource transmission block unit which is near to the front most position of the unmapped position into the resource block whose indicated value of the unmapped communication channel quality is the biggest. The method improves the decrypting accuracy of a terminal and reduces the retransmitting frequency through mapping the RB transmission unit whose position is near to the front position in the flow of signals into the RB with higher CQI value.

Apparatus, systems, and methods are disclosed, such as those that operate within a memory device to replace one or more selected failing memory cells with one or more repair memory cells and to correct data digits read from other failing memory cells in the memory device using a different method. Additional apparatus, systems, and methods are disclosed.

An INVSRC node and a SAREF node are previously precharged. After a potential on a bit line is reset, the bit line (BLS node) is precharged. In this event, a clamp MOS transistor in a sense amplifier is in ON state, and an SA node is also precharged simultaneously. A precharge level is set to a value lower than a threshold voltage of an inverter. Subsequently, when SAEN transitions to “H,” a sense operation is performed. For reading data “0,” the SA node is rapidly increased to Vdd. For reading data “1,” the SA node slowly approaches to Vss. A change in the potential at the SA node is detected by the inverter.

The invention provides a fast selection method and a fast selection device of an inter-frame prediction mode, and electronic equipment. The method comprises the steps of judging whether a current coding unit is a minimal coding unit with preset depth; if no, dividing the current coding unit into four sub-coding units; computing a rate-distortion cost of the current coding unit under a Split mode and a minimal rate-distortion cost of the current coding unit under a to-be-selected undivided mode; and determining the best prediction mode of the current coding unit according to the rate-distortioncost under the Split mode and the minimal rate-distortion cost under the to-be-selected undivided mode. According to the method provided by the invention, the best prediction mode is determined according to the rate-distortion cost under the Split mode and the minimal rate-distortion cost under the to-be-selected undivided mode, good coding quality and high coding rate can be simultaneously effectively achieved, the coding rate can be greatly improved under the premise of ensuring the coding quality, and the problem that the existing method is difficult to simultaneously achieve good coding quality and high coding rate is alleviated.

A method of input/output (I/O) assignment for a circuit design for a programmable logic device (PLD) can include determining I/O types for I/O objects specified by the circuit design, defining a plurality of virtual I/O bank-groups, wherein each virtual I/O bank-group includes at least one virtual I/O bank, and binding I/O objects of the circuit design into I/O groups according to the I/O types. A binary compatibility matrix can be created. The binary compatibility matrix can indicate the compatibility between the virtual I/O bank-groups and the I/O groups based upon the I/O types of I/O objects within each I/O group. A determination can be made as to whether a feasible solution exists for I/O assignment of the I/O objects of the circuit design according to a plurality of constraints and the binary compatibility matrix.

Persistent Memory, byte-addressable non-volatile memory technologies, offer performance advantages and access similar to Dynamic Random Access Memory while having the persistence of disk. Hardware Transactional Memory support, originally designed for DRAM concurrency control, can corrupt persistent memory transactions due to cache evictions before system failure. Unifying storage and memory on the main-memory bus and accessed directly while using HTM for concurrency control has previously required the additional burden of changes to processors to prevent possible data corruption.

The present invention provides a solution for the durability of transactions to persistent memory while using HTM as a concurrency control mechanism, without any changes to processors or cache-coherency mechanisms. The invention includes a software only method and system that provides durability and ordering of HTM transactions to persistent memory. The invention also discloses a back-end memory controller that supports HTM transactions for durability to persistent memory without up-front processor changes.

The invention provides an internal memory reforming method, an internal memory reforming device, electronic equipment and a readable storage medium. The method comprises the steps of detecting an internal memory distribution situation; judging whether an advance reforming condition is met according to the detected internal memory distribution situation; and reforming the internal memory in advance when the internal memory distribution situation meets the advance reforming condition. Therefore, the internal memory is reformed in advance before the internal memory is fragmentized, so that time-consuming internal memory reforming is avoided, when the internal memory is fragmentized, and thus user experience is enhanced.

The invention provides an MPK technology-based inter-microkernel-module communication method and system, and a medium, and the method comprises the steps: an execution domain step based on MPK technology: controlling the read-write authority of a memory domain through the MPK technology, and separating the resources and states of execution domains from each other; a checkpoint function step of communication between the kernel modules, wherein a checkpoint function modifies the read-write permission of a memory domain at the current moment through a WRPKRU instruction, and switching of an execution domain is carried out; and in the execution domain to which the kernel module of the requested service belongs, requesting the service of the kernel module in the checkpoint function in the formof function call. According to the invention, the IPC performance overhead of a microkernel is effectively reduced, and the microkernel applying the invention has the same safety guarantee as the traditional microkernel through the MPK technology.

[Problem to be Solved] To provide a communication apparatus that is novel, enhanced, and able to improve communication efficiency through improvement of an existing slice construction method. [Solution] There is provided a communication apparatus including a communication control section that performs, using a network address configured by m bytes, communication control on one or more network slices, and the network address has a prefix section that includes, in a portion of high-order n bytes, a slice number that identifies the one or more network slices and a subnet number in the one or more network slices.

The invention discloses a system and a method for processing multi-transponder programs by an integrated conditional access module; the system comprises a tuner, an FPGA, a controller, an intelligent card and a modulator; wherein the output end of the tuner is connected with the input end of the FPGA, the FPGA is connected with the controller, the controller is connected with the intelligent card, and the output end of the FPGA is connected with the modulator; the controller is used for analyzing program identifier values of the authorization control information and the authorization management information, sending effective data to the intelligent card to complete authorization and obtain control words, and sending the control words of programs to the FPGA in real time, and the FPGA is used for descrambling video and audio data; an integrated CAM board card is used, four repeaters and three intelligent cards are additionally arranged, decryption and descrambling of 56 sets of encrypted programs on the four repeaters can be completed at the same time, the processing capacity of the digital forwarding all-in-one machine is improved, and the size occupied by the decryption part of the all-in-one machine is greatly reduced.

Embodiments of the invention provide a server quiescing method and system. A server comprises a master node control domain and at least one sub-node control domain. The master node control domain comprises a master monarch processor. The sub-node control domain comprises a domain monarch processor. The method comprises the steps that: the master monarch processor sends a quiescing instruction to the domain monarch processor; the domain monarch processor forwards the quiescing instruction to a general caching proxy in the sub-node control domain in which the domain monarch processor is located; and the general caching proxy in the sub-node control domain executes the quiescing instruction.

The invention discloses an efficient keyword filtering method for FPGA (Field Programmable Gate Array) implementation, and belongs to the technical field of network security. According to the method, a keyword set is preprocessed, rapid matching can be carried out by adopting a method for carrying out hash calculation on keywords and to-be-searched data, the parallel capability of an FPGA is fully utilized, a parallel search engine is realized on the FPGA, rapid keyword search with a certain false alarm rate is carried out, and according to a feedback result searched by the FPGA, the keyword set can be quickly matched with the to-be-searched data. According to the technical scheme, accurate keyword matching searching is carried out without storing keywords on the FPGA, the parallel searching capability of FPGA hardware can be fully utilized, the characteristic that the host and the FPGA are large in off-chip storage capacity can also be utilized, the overall processing performance can reach 40 Gbps or above, and the method has the advantages of being high in searching speed, small in space consumption, free of storing the keywords and the like.

Each of memory blocks of a nonvolatile memory device includes a memory cell region including first metal pads, first memory cells of a first portion of pillar, and second memory cells of a second portion of the pillar, and a peripheral circuit region including second metal pads, a row decoder, and a page buffer. When performing program operations based on consecutive addresses at a memory block selected from the memory blocks, the nonvolatile memory device sequentially completes first program operations of non-adjacent memory cells not adjacent to a boundary of the first portion and the second portion from among the first and second memory cells and then completes a second program operation of an adjacent memory cell adjacent to the boundary. The peripheral circuit region is vertically connected to the memory cell region by the first metal pads and the second metal pads directly.

A semiconductor package includes a plurality of chips, which include a plurality of corresponding functional blocks having the same function among the chips, and only one of the corresponding functional blocks having the same function among the chips enables function, and one or more functional blocks enable function in each of the chips, so that the functional blocks are distributed among the chips.

The invention discloses a ping-pong RAM-based strip array convolution module and an operation method thereof. The convolution module comprises a direct memory access module DMA, a DMA controller, a data distribution module, a ping-pong RAM, an RAM reading module, a strip array module, a block accumulation module and a register module. The DMA controller is used for controlling DMA to read data from a memory, and the data comprises a feature and a weight; the characteristic feature and the weight weight weight of the data are separted through a data distribution module, and then the data is stored into a ping-pong RAM; the RAM reading module is used for reading features and weights from the ping-pong RAM and sending the features and the weights to the strip array module for operation processing, and an operation result is output through the block accumulation module; and the register module is used for receiving a register configured by the central processing unit to control the convolution module to operate. According to the invention, the utilization rate of the multiplier can be improved, and convolution kernels of different sizes can be compatible.

The invention provides a serial communication debugging method based on a test environment. The method comprises the following steps: installing a virtual single-chip microcomputer automatic serial port tool and a message configuration file in a computer; modifying the message configuration file according to a test environment requirement; enabling the single-chip microcomputer to be connected with a computer through a serial port line; starting an automatic serial port tool, and realizing serial port communication debugging through message automatic reply. The computer is used for simulating the MCU serial port, receiving and sending message pairs can be customized according to actual requirements, the field environment can be simulated, serial communication customized automatic reply is achieved, and follow-up debugging work is facilitated.