179 results about "Integrated circuit" patented technology

Flip-flops in a monolithic three-dimensional (3D) integrated circuit (IC)(3DIC) and related method are disclosed. In one embodiment, a single clock source is provided for the 3DIC and distributed to elements within the 3DIC. Delay is provided to clock paths by selectively controllable flip-flops to help provide synchronous operation. In certain embodiments, 3D flip-flop are provided that include a master latch disposed in a first tier of a 3DIC. The master latch is configured to receive a flip-flop input and a clock input, the master latch configured to provide a master latch output. The 3D flip-flop also includes at least one slave latch disposed in at least one additional tier of the 3DIC, the at least one slave latch configured to provide a 3DIC flip-flop output. The 3D flip-flop also includes at least one monolithic intertier via (MIV) coupling the master latch output to an input of the slave latch.

A system for stabilizing a delay through a signal path of an integrated circuit (IC) includes an oscillator for producing a periodic first reference signal, a delay circuit for delaying the first reference signal to produce a periodic second reference signal, and a loop controller for adjusting the magnitude of the IC's power supply so as to maintain a constant phase difference between the first and second reference signals. By adjusting the power supply magnitude, the loop controller also stabilizes signal path delays through logic circuits implemented in the IC. The oscillator is formed by a logic gate implemented in the IC and a passive delay line feeding the logic gate's output back to its input. The delay of the delay circuit is programmably adjustable to allow for adjustment of the signal path delay through the IC.

The configurations of an interleaved flyback converter and a controlling method thereof are provided. The proposed two-phase interleaved flyback converter includes a transformer including a first primary winding having a first terminal, a first secondary winding having a first terminal, a second primary winding having a second terminal, a second secondary winding having a second terminal and a magnetic coupled core device, wherein the first primary, the first secondary, the second primary and the second secondary windings are wound therein, and the first terminal of the first primary winding has a polarity the same as that of any of the first terminal of the first secondary winding, the second terminal of the second primary winding and the second terminal of the second secondary winding so as to eliminate a ripple of a channel current of the converter.

A semiconductor package has a printed circuit board, an integrated circuit chip on the printed circuit board with an exposed semiconductor die, and a rigid structure secured to the printed circuit board and enclosing the exposed semiconductor die. The exposed surface of the semiconductor die placed is in thermal contact with an inner surface of the rigid structure with a compressible material.

A system for creating mask layout pattern data in order to create a number of desired features on a semiconductor wafer. Critical features and features that are adjacent to or abut critical features are formed as phase shifting regions on a mask. Larger, non-critical features can be formed as annular rim shifters and may include one or more filling phase shifting regions. Non-critical features that are not adjacent to critical features and/or sub-resolution features that are not desired to print on the wafer can be formed as opaque or partially transparent regions on the mask.

Integrated circuit memory devices include an array of nonvolatile N-bit memory cells, where N is an integer greater than one. Control circuitry is also provided to reliably read data from the N-bit memory cells. This control circuitry, which is electrically coupled to the array, is configured to determine, among other things, a value of at least one bit of data stored in a selected N-bit memory cell in the array. This is done by decoding at least one hard data value and a plurality of soft data values (e.g., 6 data values) read from the selected N-bit memory cell using a corresponding plurality of unequal read voltages applied to the selected N-bit memory cell during a read operation.

Aqueous cleaning solutions are provided for cleaning an integrated circuit device formed on a wafer, as well as methods of cleaning a wafer using the aqueous cleaning solution. In one aspect, an aqueous cleaning solution includes a low foam surfactant, a metal corrosion inhibitor, an acidic pH control agent or an alkali pH control agent, and water.

A temporary chip attach carrier for and a method of testing an integrated circuit chip. The carrier includes: a substrate, a first array of interconnects disposed on a bottom surface and a second array of interconnects disposed on a top surface of the substrate, corresponding interconnects of the first and second arrays of interconnects electrically connected by wires in the substrate; an interposer, a first array of pads disposed on a top surface of the interposer and a second array of pads disposed on a bottom surface of the interposer, corresponding pads of the first and second arrays of pads electrically connected by wires in the interposer, and pads of the second array in direct physical and electrical contact with corresponding interconnects of the second set of interconnects; and wherein the interposer includes an interposer substrate of the same material as a substrate of the integrated circuit chip.

A method, apparatus, and computer program product for using a multi-core integrated circuit having cores with differing performance characteristics. The cores are arranged into high and low performance groups and tasks are assigned according to their priority to either a high or low performance group.

A method, system, and apparatus for transferring integrated circuit dies is described. A die receptacle structure has a first surface. The first surface has a plurality of cells formed therein. Each cell is configured to contain an integrated circuit die. A bottom surface of each cell is configured to attract dies having a first material thereon. Example forces that can be used to attract dies into cells include a magnetic force, a chemical force, and an electrostatic force.

An integrated circuit structure includes a semiconductor substrate; a dielectric layer over the semiconductor substrate; a conductive wiring in the dielectric layer; and a metal carbide cap layer over the conductive wiring.

Various methods and apparatuses (such as computer readable media implementing the method) are described that relate to proximate placement of sequential cells of an integrated circuit netlist. For example, the preliminary placement is received; and based on the preliminary placement, a group of sequential cells is identified as being subject to improved power and/or timing upon subsequent placement. In another example, identification is received of a group of sequential cells subject to improved power and/or timing upon subsequent placement; and proximate placement is performed of the identified group of sequential cells. In yet another example, a proximate arrangement of a group of sequential cells is received; and if proximate placement fails, then the group of sequential cells is disbanded and placement is performed of the sequential cells of the disbanded group.

A storage cell that may be a memory cell, and integrated circuit (IC) chip including an array of the memory cells and a method of forming the IC. Each storage cell is formed between a top an bottom electrode. Each cell includes a phase change layer that may be a chalcogenide and in particular a germanium (Ge), antimony (Sb), tellurium (Te) or GST layer. The cell also includes a stylus with the apex of the stylus contacting the GST layer. The apex may penetrate the GST layer

A system and method of assembling a ball grid array (BGA) package with IC die support is described. A stiffener is attached to a substrate that includes a centrally located opening with an integrated circuit (IC) die support structure removably held therein. An IC die is mounted to a central region of the stiffener. Further assembly process steps may be performed on the BGA package with IC die support. The IC die support structure is removed from the centrally located opening. In aspects of the invention, the IC die support structure is removably held in the opening by an adhesive tape or by one or more substrate tabs.

A semiconductor integrated circuit having a built-in PLL circuit which has two charge pump circuits for charging and discharging capacitive elements of a loop filter in response to signals generated by a phase comparator circuit. One of the two charge pump circuits has current sources which generate current values smaller than those generated by current sources of the other charge pump circuit. The loop filter has a first capacitive element connected to a charge/discharge node, and a second capacitive element connected to the charge/discharge node through a resistive element. The first capacitive element is charged and discharged by the one charge pump circuit, while the second capacitive element is charged and discharged by the other charge pump circuit. A charging current source of the one charge pump circuit operates simultaneously with a discharging current source of the other charge pump circuit, i.e., the charge pump circuits operate in opposite phase.

A method is provided to select circuit cells for use in optimization of an integrated circuit design from among a plurality of circuit cells within a cell library, the method comprising: obtaining a value for each cell of the plurality that is indicative of both the cell's power dissipation and the cell's rate of output voltage change; ordering the cells of the plurality based upon the values; identifying a difference between values of cells that are proximate each other within the ordering of the cells that meets a threshold; and designating a cut point within the ordering of the cells based upon the identified difference.

The invention discloses a preparation method for a photolithographic alignment mark. The method is used for preparing the photolithographic alignment mark on a silicon substrate and comprises the following steps: preparing an oxidation layer on the silicon substrate; carrying out the photolithography and development through photoresist and retaining the photoresist at the position of the photolithographic alignment mark; taking the formed photoresist pattern as a photolithographic masking plate so as to etch and expose the oxidation layer to the silicon surface, and finally removing the photoresist layer; and carrying out the silicon epitaxy growth to make the surface height of the epitaxial layer higher than that of the oxidation layer and form the photolithographic alignment mark. The preparation method avoids the problem of a fuzzy mark caused by the thickened epitaxial layer in the prior method for the photolithographic alignment mark based on ditch groove etching. Simultaneously, the method has the advantages of low manufacturing cost, simple process control, extended process capability window, and high alignment accuracy. The method is applied to the manufacturing of integrated circuits.

A display device includes a display panel including a pixel array including data lines, gate lines crossing the data lines, and pixels arranged in a matrix form, a source driver integrated circuit (IC) for supplying a data voltage to the data lines, a gate driver IC for supplying a gate pulse to the gate lines, and a first flexible film cable bonded to a substrate of the display panel. The first flexible film cable includes lines for transmitting gate timing control signals and gate driving powers received from a printed circuit board to the gate driver IC. The first flexible film cable has a thickness of about 20 μm to 100 μm.

The invention discloses a communicating system apparatus and detecting method thereof. The apparatus includes an on-line testing controller, connected to a master control board for managing a testing database, wherein the controller is used for distributing testing data and transmitting testing data sequences to apparatus boards through the master control board, or colleting testing data sequences from apparatus boards; and board external testing interfaces, respectively set up on the back board in one-to-one correspondence with the plurality of apparatus boards, wherein, on-line testing terminal ports of integrated circuit chips on each apparatus are connected in series to form a board on-line testing chain, the input-output terminal ports of the board on-line testing chain are connected onto the back board and the board external testing interface corresponding to the apparatus board. The invention can perform on-line or periodically failure testing and locating to the communicating system apparatus, preventing and maintaining the probable existing faults beforehand, thereby improving reliability of the communicating system apparatus.

The circuits and methods are provided for impedance termination on an integrated circuit. A network of resistors are formed on an integrated circuit (IC) to provide on-chip impedance termination to differential input/output (IO) pins. Transistors are coupled in the network of termination resistors. The transistors provide additional termination impedance to the differential IO pins. The transistors can be turned ON or OFF separately to change the impedance termination.

An integrated circuit (IC) chip module includes at least one integrated circuit chip mounted upon a substrate, and a plurality of passive components mounted upon the substrate. A polymer based bib has at least one opening formed therein, the at least one opening configured to accommodate the at least one integrated circuit chip therein, and the bib further configured for attachment to one or more of the plurality of passive components. A protective cap is mounted over the at least one integrated circuit chip and attached to the substrate, wherein the bib is configured to retain thereon a thermally conductive paste initially applied to at least one of the integrated circuit chip and the protective cap.

A surface mount grid array implemented on a PCB (printed circuit board) optimized for trace escape routing for the PCB. The surface mount grid array includes a plurality of connection blocks, with each connection block including an array of pins and an array of vias, wherein the pins and vias are configured to communicatively connect an integrated circuit device to a plurality of traces of the PCB. The connection blocks are disposed in a tiled arrangement, wherein the connection blocks implement a plurality of trace escape channels along connection block boundaries. The trace escape channels are configured for routing traces from inner pins of the surface mount grid array to a periphery of the surface mount grid array.