132results about "Transistor" patented technology

The present invention provides a field effect transistor including an oxide film as a semiconductor layer, wherein the oxide film includes one of a source part and a drain part to which one of hydrogen and deuterium is added.

In semiconductor devices in which both NMOS devices and PMOS devices are used to perform in different modes such as analog and digital modes, stress engineering is selectively applied to particular devices depending on their required operational modes. That is, the appropriate mechanical stress, i.e., tensile or compressive, can be applied to and/or removed from devices, i.e., NMOS and/or PMOS devices, based not only on their conductivity type, i.e., n-type or p-type, but also on their intended operational application, for example, analog/digital, low-voltage/high-voltage, high-speed/low-speed, noise-sensitive/noise-insensitive, etc. The result is that performance of individual devices is optimized based on the mode in which they operate. For example, mechanical stress can be applied to devices that operate in high-speed digital settings, while devices that operate in analog or RF signal settings, in which electrical noise such as flicker noise that may be introduced by applied stress may degrade performance, have no stress applied.

A semiconductor device includes a semiconductor substrate including a main surface; a plurality of first interconnections formed in a capacitance forming region defined on the main surface and extending in a predetermined direction; a plurality of second interconnections each adjacent to the first interconnection located at an edge of the capacitance forming region, extending in the predetermined direction, and having a fixed potential; and an insulating layer formed on the main surface and filling in between each of the first interconnections and between the first interconnection and the second interconnection adjacent to each other. The first interconnections and the second interconnections are located at substantially equal intervals in a plane parallel to the main surface, and located to align in a direction substantially perpendicular to the predetermined direction.

The invention enhances a production yield of a display device (an electro-optical device). The invention provides a method of manufacturing an electro-optical device including a display region in which a plurality of basic pixels are arranged, each basic pixel including a plurality of color pixels. The method includes: forming on a first substrate lines to drive a plurality of electro-optical elements respectively constituting the color pixels, correspondingly to the arrangement of the basic pixels; forming on a second substrate, as a chip to be transferred to each basic pixel, a drive circuit to drive the plurality of electro-optical elements which constitutes the plurality of color pixels of the basic pixels to obtain a plurality of basic-pixel driving chips; and transferring step of transferring the respective basic-pixel driving chips from the second substrate onto the first substrate, and connecting the drive circuits to regions of the lines corresponding to the basic pixels.

There is provided a thin film transistor having improved reliability. A gate electrode includes a first gate electrode having a taper portion and a second gate electrode with a width narrower than the first gate electrode. A semiconductor layer is doped with phosphorus of a low concentration through the first gate electrode. In the semiconductor layer, two kinds of n⁻-type impurity regions are formed between a channel formation region and n⁺-type impurity regions. Some of the n⁻-type impurity regions overlap with a gate electrode, and the other n⁻-type impurity regions do not overlap with the gate electrode. Since the two kinds of n⁻-type impurity regions are formed, an off current can be reduced, and deterioration of characteristics can be suppressed.

The present invention describes a transistor based on a Hetero junction FET structure, where the metal gate has been replaced by a stack formed by a highly doped compound semiconductor and an insulating layer in order to achieve enhancement mode operation and at the same time drastically reduce the gate current leakage. The combination of the insulating layer with a highly doped semiconductor allows the tuning of the threshold voltage of the device at the desired value by simply changing the composition of the semiconductor layer forming the gate region and/or its doping allowing a higher degree of freedom. In one of the embodiment, a back-barrier layer and a heavily doped threshold tuning layer are used to suppress Short Channel Effect phenomena and to adjust the threshold voltage of the device at the desired value. The present invention can be realized both with polar and non-polar (or semi-polar) materials.

A self-aligned gate cap dielectric can be employed to form a self-aligned contact to a diffusion region, while preventing electrical short with a gate conductor due to overlay variations. In one embodiment, an electroplatable or electrolessly platable metal is selectively deposited on conductive materials in a gate electrode, while the metal is not deposited on dielectric surfaces. The metal portion on top of the gate electrode is converted into a gate cap dielectric including the metal and oxygen. In another embodiment, a self-assembling monolayer is formed on dielectric surfaces, while exposing metallic top surfaces of a gate electrode. A gate cap dielectric including a dielectric oxide is formed on areas not covered by the self-assembling monolayer. The gate cap dielectric functions as an etch-stop structure during formation of a via hole, so that electrical shorting between a contact via structure formed therein and the gate electrode is avoided.

The present invention discloses a thin film transistor and a method of fabricating the same. The thin film transistor includes an insulating substrate; and a semiconductor layer, a gate insulating layer, a gate electrode, an interlayer insulator, and a source/drain electrode which are formed on the substrate, wherein the gate insulating layer is formed of a filtering oxide layer having a thickness of 1 to 20 Å.

In a first structure, a metal gate portion may be laterally recessed from a substantially vertical surface of a gate conductor thereabove. A cavity is formed between the metal gate portion and a gate spacer. In a second structure, a disposable gate portion is removed after laterally recessing a metal gate portion therebeneath and forming a dielectric layer having a surface coplanar with a top surface of the disposable gate portion. (We have to include the inner spacer without a metal recess). An inner gate spacer is formed over a periphery of the metal gate portion provide a reduced overlap capacitance. In a third structure, a thin dielectric layer is employed to form a cavity next to the metal gate portion in conjunction with the inner gate spacer to provide reduced overlap capacitance.

Transistor bodies of semiconductor material located at a main surface of a semiconductor substrate between shallow trench isolations are provided with a rounded or curved upper surface. A floating gate electrode is arranged above said upper surface and electrically insulated from the semiconductor material by a tunnel dielectric having essentially the same tiny thickness throughout a primary tunnel area encompassing the area of curvature. The floating gate electrode may bridge the transistor body and is covered with a coupling dielectric provided for a control gate electrode, which forms part of a wordline.

There are provided a MOS transistor having a double gate and a manufacturing method thereof. The MOS transistor includes a substrate on which an insulating layer is formed, a first gate embedded in the insulating layer, in which the top surface of the first gate is exposed, a first gate oxide layer formed on the insulating layer and the first gate, a silicon layer formed on the first gate oxide layer, a source region and a drain region formed in the silicon layer to be in contact with the first gate oxide layer, a second gate oxide layer formed on the silicon layer to be in contact with the source and drain regions, and a second gate formed on the second gate oxide layer disposed between the source region and the drain region.

BiFeO₃ precursor solution is coated on the surface of an underlying member. Teat treatment is performed after the coating to form a dielectric film. The dielectric film is heated in a non-oxidizing atmosphere to crystallize the dielectric film. With this method, a ferroelectric material can be obtained which contains constituent elements of Bi, Fe and O and has crystal lattice of a tetragonal or orthorhombic system.

It is an object to provide a semiconductor device for high power application which has good properties. A means for solving the above-described problem is to form a transistor described below. The transistor includes a source electrode layer; an oxide semiconductor layer in contact with the source electrode layer; a drain electrode layer in contact with the oxide semiconductor layer; a gate electrode layer part of which overlaps with the source electrode layer, the drain electrode layer, and the oxide semiconductor layer; and a gate insulating layer in contact with an entire surface of the gate electrode layer.

A highly reliable semiconductor device is provided. A semiconductor device is manufactured at a high yield, so that high productivity is achieved. In a semiconductor device including a transistor in which a gate electrode layer, a gate insulating film, an oxide semiconductor film containing indium, and an insulating layer provided on and in contact with the oxide semiconductor film so as to overlap with the gate electrode layer are stacked and a source electrode layer and a drain electrode layer are provided in contact with the oxide semiconductor film and the insulating layer, the chlorine concentration and the indium concentration on a surface of the insulating layer are lower than or equal to 1×10¹⁹/cm³ and lower than or equal to 2×10¹⁹/cm³, respectively.

A conventionally followed technique of manufacturing a liquid crystal display device is a method for forming various types of coatings over an entire surface of a substrate and for removing the coatings with a small region left by etching, which requires wasting a material cost and treating a large quantity of waste. A liquid crystal display device is manufactured by forming at least one or more of patterns necessary for manufacturing a liquid crystal display device by a method capable of selectively forming a pattern. A droplet discharge method capable of forming a predetermined pattern by selectively discharging a droplet of a composition prepared for a specific purpose is employed as the method capable of selectively forming a pattern.

A non-volatile memory device including a memory string including a plurality of memory cells coupled in series. The non-volatile memory device includes the memory string including a first semiconductor layer and a second conductive layer with a memory gate insulation layer therebetween, a first selection transistor comprising a second semiconductor layer coupled with one end of the first semiconductor layer, a second selection transistor comprising a third semiconductor layer coupled with the other end of the first semiconductor layer, and a fourth semiconductor layer contacting the first semiconductor layer in a region where the second conductive layer is not disposed.

The invention provides a preparation method of a top gate metal oxide thin film transistor (TFT), belonging to the technical field of semiconductors. The method comprises the following steps: preparing a source/drain electrode; then preparing a metal oxide material; coating a photoresist on the surface of the metal oxide material and carrying out chemical mechanical polishing on the photoresist layer; processing the metal oxide which is not masked by the photoresist by annealing or plasmas; and finally stripping the photoresist and depositing a gate insulation layer material through magnetronsputtering and forming a gate through wet etching. The method has the following beneficial effects: reliable ohmic contact between the metal oxide thin film and the source/drain electrode can be formed by utilizing the characteristic that the metal oxide material can be converted into a conductor from a semiconductor after undergoing special processing.

A MOSFET device and a method of fabricating a MOSFET device having low-K dielectric oxide gate sidewall spacers produced by fluorine implantation. The present invention implants fluorine into the gate oxide sidewall spacers which is used to alter the properties of advanced composite gate dielectrics e.g. nitridized oxides, NO, and gate sidewall dielectrics, such that the low-K properties of fluorine are used to develop low parasitic capacitance MOSFETs.

A semiconductor device includes an active layer, a source electrode, a drain electrode, a gate electrode, an interlayer dielectric, an inter-source layer, an inter-source plug, an inter-drain layer, an inter-drain plug, an inter-gate layer, and an inter-gate plug. The active layer is made of III-V group semiconductors. The source electrode, the drain electrode, and the gate electrode are disposed on the active layer. The gate electrode is disposed between the source electrode and the drain electrode. The interlayer dielectric covers the source electrode, the drain electrode, and the gate electrode. The inter-source layer, the inter-drain layer, and the inter-gate layer are disposed on the interlayer dielectric. The inter-source plug is electrically connected to the source electrode and the inter-source layer. The inter-drain plug is electrically connected to the drain electrode and the inter-drain layer. The inter-gate plug is electrically connected to the gate electrode and the inter-gate layer.

In order to transmit high-speed digital signals of several tens of GHz through differential lines, a signal transmission system for transmitting digital signals between circuit blocks via signal transmission lines is provided by connecting a ground-referenced differential line to a non-ground-referenced differential line, Each circuit block basically includes a functional circuit, a receiving/transmitting circuit formed separately from the functional circuit, and an impedance-matched transmission line (115) formed between the receiving end and the transmitting end of the receiving/transmitting circuit; reference ground (110) The differential line (105) is drawn from the differential output driver, and a differential signal line is formed symmetrically with respect to the ground (110) in the circuit block. In the signal transmission line (115), there are only differential pair lines that are not referenced to ground (111, 112) extend directly from differential signal lines arranged symmetrically with respect to ground potential.

A liquid crystal display device of so-called an In-Plane Switching mode in which an electric field substantially parallel to substrates is applied to a liquid crystal layer by applying a voltage between a pixel electrode and a common electrode is disclosed. In the liquid crystal display device, a source line is overlapped with a part of a common electrode with an insulation film interposed therebetween. The insulation film has a plurality of layers of insulation films.

To provide a method for manufacturing a large semiconductor device which easily operates normally and has excellent current characteristics. A first single-crystal semiconductor layer is provided over an insulating substrate. Then, the first single-crystal semiconductor layer is processed into an island shape. After that, a second single-crystal semiconductor layer is provided over the insulating substrate so as to overlap with part of a region where the first single-crystal semiconductor layer is provided. After that, the second single-crystal semiconductor layer is processed into an island shape. Thus, defects at joint portions in the case of providing the single-crystal semiconductor layers can be reduced.

To improve the reliability of a semiconductor device including a low-resistance material such as copper, aluminum, gold, or silver as a wiring. Provided is a semiconductor device including a pair of electrodes electrically connected to a semiconductor layer which has a stacked-layer structure including a first protective layer in contact with the semiconductor layer and a conductive layer containing the low-resistance material and being over and in contact with the first protective layer. The top surface of the conductive layer is covered with a second protective layer functioning as a mask for processing the conductive layer. The side surface of the conductive layer is covered with a third protective layer. With this structure, entry or diffusion of the constituent element of the pair of conductive layers containing the low-resistance material into the semiconductor layer is suppressed.

A silicon on insulator shaped structure formed to reduce floating body effect comprises a T-shaped active structure and a body contact for back bias. Etching a T-shape through two layers of oxide will form the T-shaped active areas. A back bias is formed when a metal line is dropped through the SOI structure and reaches a contact plug. This contact plug is doped with N+ or P+ dopant and is embedded in a Si substrate. The T-active shaped structure is used to reduce the short channel effects and junction capacitance that normally hinder the effectiveness of bulk transistors. The back bias is used as a conduit for generated holes to leave the SOI transistor area thus greatly reducing the floating effects generally associated with SOI structures.