30 results about "Polycrystalline silicon" patented technology

A solar cell includes a doped layer disposed on a first surface of a semiconductor substrate, a doped polysilicon layer disposed in a first region of a second surface of the semiconductor substrate, a doped area disposed in a second region of the second surface, and an insulating layer covering the doped polysilicon layer and the doped area. The insulating layer has openings exposing portions of the doped polysilicon layer and the doped layer, and the doped polysilicon layer and doped layer are respectively connected to a first electrode and a second electrode through the openings. The semiconductor substrate and the doped layer have a first doping type. One of the doped polysilicon layer and the doping area has a second doping type, and the other one of the doped polysilicon layer and the doping area has the first doping type which is opposite to the second doping type.

Different types of thin film transistors are disposed on the same flexible substrate and an organic light emitting display using the same includes a display area and a non-display area; a first buffer layer over an entire surface of the flexible substrate; a driving transistor on the buffer layer in the display area, the driving transistor including a polycrystalline silicon (LIPS) layer, a first gate electrode, a first source electrode, and a first drain electrode; a capacitor electrode on the first source electrode of the driving transistor and forming a storage capacitor together with the first source electrode; a switching transistor in the display area to be spaced apart from the driving transistor; and a dummy electrode on the switching transistor, the dummy electrode formed of the same material as the capacitor electrode, and disposed on the same plane as the capacitor.

The invention discloses a novel design method for ESD protection, which comprises the following steps: (1) forming a well region, a gate oxide layer, gate poly-silicon, a porous medium layer, a source electrode and a grid electrode on a silicon substrate of a DMOS device in order; (2) forming the gate poly-silicon under lead bores of the source electrode and the grid electrode; and (3) forming the gate oxide layer between the gate poly-silicon and the well region, wherein the gate oxide layer is used for isolating the source electrode and the grid electrode when the lead bores of the source electrode and the grid electrode are punched at the position of the gate poly-silicon. The novel design method has the remarkable characteristics of utilizing the same set of MASK to produce products with ESD or without ESD by selecting whether to increase a process for photoetching an ESD layer, so as to save MASK cost and greatly save the production cost of the products.

Methods of forming a cell pad contact hole on an integrated circuit include forming adjacent gates on an integrated circuit substrate having a source/drain region extending between the gates. Gate spacers are formed on facing sidewalls of the adjacent gates. A cell pad contact hole is formed aligned to the gates and gate spacers that exposes the source/drain region in the integrated circuit substrate. A first poly film is formed in the cell pad contact hole. An ion region is formed in the source/drain region by ion-implanting through the first poly film and a second poly film is formed on the first poly film that substantially fills the cell pad contact hole.

Embodiments of the present invention provide a single crystal pulling device, a preparation method of single crystal silicon, and the single crystal silicon. The single crystal pulling device includesa housing, a melting member and a blocking member; the housing is provided with a receiving space, the receiving space includes at least a first chamber and a second chamber communicating with the first chamber, and the second chamber is located above the first chamber; the melting member is used for heating and melting polysilicon, and the melting member is fixed to the bottom of the first chamber; and the blocking member is located in the second chamber, and the blocking member is used for injecting an inert gas in a preset manner to prevent impurities generated by the polysilicon melting process from entering the upper chamber of the second chamber. With the single crystal pulling device disclosed by the embodiments of the invention, a large amount of impurities can be prevented from flowing into the upper chamber of the single crystal pulling device, thereby reducing the dislocation problem of a single crystal silicon rod caused by impurities, improving the crystal quality, and also facilitating the cleaning work of the receiving space.

The invention discloses a dissociation-solidification abrasive particle composite wire saw cutting method for photovoltaic polycrystalline silicon cells. The method comprises the following steps: (1)photovoltaic polycrystalline silicon workpieces are cut through a sawing wire; (2) mortar with dissociated silicon carbide abrasive particles is sprayed to a cutting area; and the dissociated siliconcarbide abrasive particles are distributed and constrained in a spiral baked wire area without solidified abrasive particles on the surface of the sawing wire; and (3) in the sawing process, the photovoltaic polycrystalline silicon workpieces are cut by the sawing wire; and meanwhile, the dissociated silicon carbide abrasive particles in the mortar are constrained in the spiral baked wire area onthe surface of the sawing wire under movement of the sawing wire to grind a cutting surface to cut the photovoltaic polycrystalline silicon cells. The method adopts the dissociated abrasive particle and solidified abrasive particle composite wire saw cutting to grind the surfaces of slices during slicing, and removes cutting line marks and plastic smooth areas on the surfaces of the slices causedby solidification abrasive particle wire saw cutting to form microstructures similar to the surfaces of the dissociated abrasive particle wire saw slices on the surfaces of the slices.

The invention provides a semiconductor device and a semiconductor device fabrication method. The semiconductor device includes as a resistance element a first polycrystalline silicon and a second polycrystalline silicon containing impurities, such as boron, of the same kind and having different widths. The first polycrystalline silicon contains the impurities at a concentration CX. The second polycrystalline silicon has a width larger than a width of the first polycrystalline silicon and contains the impurities of the same kind at a concentration CY lower than the concentration CX. A sign of a temperature coefficient of resistance (TCR) of the first polycrystalline silicon changes at the concentration CX. A sign of a TCR of the second polycrystalline silicon changes at the concentration CY. A change in the resistance value of the resistance element caused by the operation of the semiconductor device and deterioration in the performance of the semiconductor device caused by the change in the resistance value of the resistance element are suppressed.

The invention provides a high-voltage PMOS transistor in a low-voltage process, and belongs to the technical field of a semiconductor integrated circuit. The transistor comprises a P type substrate PSUB, an N type well NWELL, a P type well PWELL, a first P type doped P+1, a second P type doped P+2 and polysilicon POLY. On the basis of the conventional low-voltage PMOS transistor, the P type well PWELL is added to the periphery of the second P type doped P+2, so that the second P type doped P+2 can be not in direct contact with the N type well NWELL; and by virtue of the doping characteristic of a diode, the reverse breakdown voltage of a parasitic PN junction diode formed by the second P type doped P+2 and the N type well NWELL is far lower than that of a parasitic PN junction diode formed by the P type well PWELL and the N type well NWELL, so that the drain D of the device can bear a higher voltage compared with the drain of a low-voltage device, and application requirements of many high-voltage occasions can be satisfied.

The invention discloses an efficient and safe transfer device for polycrystalline silicon ingots. The efficient and safe transfer device comprises a bottom plate. Universal wheels are installed at thebottom of the bottom plate. A pushing handle is fixedly connected to one side of the bottom plate; the bottom of the bottom plate is fixedly connected with two side plates. A sliding plate is fixedlyconnected between the two side plates; a limiting groove is formed in the sliding plate; the top of the sliding plate is fixedly connected with an electric reel; limiting plates are fixedly connectedto the two sides of the top of the bottom plate. The inner wall of the limiting plate is fixedly connected with a plurality of wheel carriers; the tail end of each wheel carrier is movably connectedwith a roller; a transfer frame is arranged above the bottom plate; a bearing plate is arranged in the transfer frame; springs are fixedly connected to the two sides of the bottom of the bearing plate, stabilizing mechanisms are arranged on the two sides of the bottom of the transfer frame, two mounting bases are fixedly connected to the bottom of the transfer frame, lifting rods are movably connected to the mounting bases, sliding grooves are formed in the bottom plate, the bottom ends of the lifting rods penetrate through limiting shafts, and pull ropes are fixedly connected to the side walls of the bottom ends of the two lifting rods.

The invention discloses a semiconductor device with a Schottky metal junction and a manufacturing method thereof. The semiconductor device comprises a substrate and an epitaxial layer formed on the surface of the substrate, a plurality of grooves are formed in the epitaxial layer, and each groove is filled with polycrystalline silicon. A gate oxide layer is formed between the polycrystalline silicon and the trench, a first metal layer is formed on the upper surface of the polycrystalline silicon, a second metal layer is formed on the upper surface, adjacent to the polycrystalline silicon, of the epitaxial layer, the first metal layer is further formed on the upper surface of the epitaxial layer, and a Schottky barrier formed by the second metal layer and the epitaxial layer is different from a Schottky barrier formed by the first metal layer and the epitaxial layer in size. According to the invention, two different barrier metals are used as Schottky contacts, when the device is reversely blocked, the Schottky barrier current is reduced by using the electric field shielding effect of the high-barrier Schottky metal on the low-barrier Schottky metal, and when the device is positively conducted, the device has relatively low conduction voltage drop due to the low-barrier Schottky metal.

The invention discloses a method for controlling the terminal by using chlorine trifluoride to etch a polysilicon growth furnace, and at least a temperature detecting device is arranged inside the polysilicon growth furnace. The method comprises the following steps of: firstly, setting a reaction temperature and a warning temperature inside the polysilicon growth furnace, introducing chlorine trifluoride gas to the inside of the polysilicon growth furnace, and continuously introducing the gas to a pre-etching time; and secondly, monitoring the temperature detecting device inside the polysilicon growth furnace, and stopping introducing the gas after continuously passing the etching time when the temperature inside the polysilicon growth furnace increases from the warning temperature and falls back to the warning temperature. The method can be adopted to discover the reaction terminal of the chlorine trifluoride and the polysilicon, thereby avoiding waste of the chlorine trifluoride gas.

The invention discloses a method for processing a semiconductor chip. The method comprises that: pollutants attached on the semiconductor chip are removed so that the cleaned semiconductor chip is acquired; and the mixed gas meeting the first preset condition is piped into a finishing stove in which the cleaned semiconductor chip is positioned so that a dangling bond at the interface of a gate electrode oxide layer and poly-silicon in the semiconductor chip is adjusted into a silicon hydrogen bond, wherein the mixed gas comprises nitrogen and hydrogen.

A polycrystalline silicon material for producing silicon single crystal, containing a plurality of polycrystalline silicon chunks, in which assuming that a total concentration of donor elements present inside a bulk body of the polycrystalline silicon material is Cd1 [ppta], a total concentration of acceptor elements present inside the bulk body of the polycrystalline silicon material is Ca1 [ppta], a total concentration of the donor elements present on a surface of the polycrystalline silicon material is Cd2 [ppta], and a total concentration of the acceptor elements present on the surface of the polycrystalline silicon material is Ca2 [ppta], Cd1, Ca1, Cd2, and Ca2 satisfy a relation of 2 [ppta]≤(Cd1+Cd2)−(Ca1+Ca2)≤8 [ppta].

The invention belongs to the technical field of semiconductor manufacturing and relates to a method for manufacturing a high-frequency silicon capacitor. The method includes etching a plurality of trenches on a substrate, forming an HfO2 dielectric layer by atomic deposition technology, depositing polycrystalline silicon on the surface of the HfO2 dielectric layer, etching to form vias, depositingan insulating layer, etching to form metal contact vias, and sputtering metal to form electrodes. The method of the invention adopts the latest atomic deposition technology to manufacture the HfO2 dielectric layer, so that the frequency characteristic of the silicon capacitor is superior to that of the traditional capacitor, the reliability is high, the capacitance precision of the capacitor is greatly improved, and the finished product rate is improved.

This invention discloses a large power MOS transistor and its process method with multi-silicon grating larger than silicon plane and simple process, which is based on the current process and removes the step two and three into the last two steps for operation to realize the process. This invention improves the multiple silicon shape to remain and improve the frequency characteristics.

The invention provides a method for preparing a 3D surrounding gate MOS transistor, comprising the steps of: forming an N-type well and a P-type well isolated by a shallow trench isolation structure on a silicon substrate; Silicon nanowires are grown on the region to form NPN nanowires and PNP nanowires respectively; after continuing to deposit an oxide isolation layer and planarize, remove the oxide isolation layer located in the middle; sequentially deposit the gate oxide layer and polysilicon , and after etching away the polysilicon located between the NPN nanowire and the PNP nanowire, deposit an oxide isolation layer; remove part of the oxide isolation layer to expose part of the polysilicon covering the NPN nanowire and the PNP nanowire, and The exposed polysilicon is removed; after the oxide isolation layer is deposited again, the source, drain and gate are prepared to form a MOS transistor. The method is easy to operate, improves the control ability of the gate to the channel and improves the performance of the device.

The invention relates to a silicon crystal clamping tool and a silicon crystal cutoff machine. The silicon crystal clamping tool comprises a working table and a silicon crystal clamping mechanism. Theworking table comprises an operation platform, a locating plate and base plates. The operation platform is provided with an operation table face. The locating plate is vertically arranged on one sideedge of the operation table face. At least two sunk grooves are formed in the operation table face. The base plates are arranged in the sunk grooves, and the upper surfaces of the base plates are located at the same horizontal height. Overflow grooves are further formed in the operation table face and arranged around the base plates. The overflow grooves are communicated and provided with overflow holes. An avoiding through groove is formed in the operation platform. The silicon crystal clamping mechanism is arranged on the working table face. The silicon crystal clamping tool is simple in structure and good in universality, single crystal silicon rods and polycrystalline silicon blocks can be stably clamped, and the equipment utilization rate and the working efficiency are high.

The invention discloses a method and a device for producing granular polysilicon by utilizing the fluidized-bed process. Hydrogen chloride is fed into a fluidized-bed reactor from an expanding section of the top of a fluidized bed and is reacted with fine silicon powder generated in the process of producing granular silicon to generate chloro-silicane gas so that risks of harm to a system due to the fact that the fine silicon powder enters a pipeline at the rear end of the fluidized bed are eliminated, fine silicon powder entrainment is eliminated simultaneously, gas inlet flow of the fluidized bed is improved so as to improve unit capacity of the rector, and production cost is lowered. Besides, the hydrogen chloride fed into the fluidized-bed reactor from the top is reacted with the fine silicon powder to generate chloro-silicane so that circulation of a certain amount of chloride in the reactor is achieved.

The invention discloses a grinding process for a polycrystalline silicon layer. The grinding process comprises the following steps: 1) measuring the thickness of a wafer; 2) performing chemical mechanical grinding on the polycrystalline silicon layer of the wafer to obtain a grinding surface; 3) carrying out RCA cleaning on the grinding surface; 4) polishing and grinding the grinding surface; (5) CPC cleaning is conducted on the grinding face; and 6) measuring the thickness of the wafer again. The grinding process can effectively reduce the bulge defects randomly distributed on the surface of the polycrystalline silicon. The invention also provides a wafer prepared by using the grinding process.