324 results about "Semiconductor" patented technology

The present invention provides a field effect transistor including an oxide film as a semiconductor layer, wherein the oxide film includes one of a source part and a drain part to which one of hydrogen and deuterium is added.

A wafer-supporting device for supporting a wafer thereon adapted to be installed in a semiconductor-processing apparatus includes: a base surface; and protrusions protruding from the base surface and having rounded tips for supporting a wafer thereon. The rounded tips are such that a reverse side of a wafer is supported entirely by the rounded tips by point contact. The protrusions are disposed substantially uniformly on an area of the base surface over which a wafer is placed, wherein the number (N) and the height (H [μm]) of the protrusions as determined in use satisfy the following inequities per area for a 300-mm wafer:

(−0.5N+40)≦H≦53; 5≦N<100.

An Advanced Process Control (APC) system including Graphical User Interfaces (GUIs) is presented for monitoring and controlling a semiconductor manufacturing process that is performed by a semiconductor processing system. The semiconductor processing system includes a number of processing tools, a number of processing modules (chambers), and a number of sensors, and the APC system comprises an APC server, database, interface server, client workstation, and GUI component. The GUI is web-based and is viewable by a user using a web browser.

A reactor for processing a substrate includes a first housing defining a processing chamber and supporting a light source and a second housing rotatably supported in the first housing and adapted to rotatably support the substrate in the processing chamber. A heater for heating the substrate is supported by the first housing and is enclosed in the second housing. The reactor further includes at least one gas injector for injecting at least one gas into the processing chamber onto a discrete area of the substrate and a photon density sensor extending into the first housing for measuring the temperature of the substrate. The photon density sensor is adapted to move between a first position wherein the photon density sensor is directed to the light source and a second position wherein the photon density sensor is positioned for directing toward the substrate. Preferably, the communication cables comprise optical communication cables, for example sapphire or quartz communication cables. A method of processing a semiconductor substrate includes supporting the substrate in a sealed processing chamber. The substrate is rotated and heated in the processing chamber in which at least one reactant gas is injected. A photon density sensor for measuring the temperature of the substrate is positioned in the processing chamber and is first directed to a light, which is provided in the chamber for measuring the incident photon density from the light and then repositioned to direct the photon density sensor to the substrate to measure the reflection of the light off the substrate. The incident photon density is compared to the reflected light to calculate the substrate temperature.

A micromachined acoustic transducer comprising a parylene diaphragm piezoelectric transducer. The parylene diaphragm has far lower stiffness than the silicon nitride. The method for fabricating the parylene diaphragm acoustic transducer utilizes a prestructured disphragm layer utilizing silicon nitride which is compatible with high temperature semiconductor process. A silicon nitride layer is patterned and partially removed after forming the parylene diaphragm layer in order to enhance the structural qualities of the parylene diaphragm. The diaphragm may be flat or dome-shaped.

In semiconductor devices in which both NMOS devices and PMOS devices are used to perform in different modes such as analog and digital modes, stress engineering is selectively applied to particular devices depending on their required operational modes. That is, the appropriate mechanical stress, i.e., tensile or compressive, can be applied to and/or removed from devices, i.e., NMOS and/or PMOS devices, based not only on their conductivity type, i.e., n-type or p-type, but also on their intended operational application, for example, analog/digital, low-voltage/high-voltage, high-speed/low-speed, noise-sensitive/noise-insensitive, etc. The result is that performance of individual devices is optimized based on the mode in which they operate. For example, mechanical stress can be applied to devices that operate in high-speed digital settings, while devices that operate in analog or RF signal settings, in which electrical noise such as flicker noise that may be introduced by applied stress may degrade performance, have no stress applied.

A semiconductor device includes a semiconductor substrate including a main surface; a plurality of first interconnections formed in a capacitance forming region defined on the main surface and extending in a predetermined direction; a plurality of second interconnections each adjacent to the first interconnection located at an edge of the capacitance forming region, extending in the predetermined direction, and having a fixed potential; and an insulating layer formed on the main surface and filling in between each of the first interconnections and between the first interconnection and the second interconnection adjacent to each other. The first interconnections and the second interconnections are located at substantially equal intervals in a plane parallel to the main surface, and located to align in a direction substantially perpendicular to the predetermined direction.

An improved method of in-situ conditioning of a polishing pad for use with a stationary pad conditioner during chemical mechanical polishing is described. A polishing table having a polishing pad on its surface is rotated in a first direction during polishing of a semiconductor wafer. A polishing pad conditioner is adjustably attached to the rotating polishing table such that the conditioner is stationary in relation to the rotating polishing table. The conditioner has a roughened surface which is in contact with the polishing pad providing in-situ conditioning during polishing of a semiconductor wafer. After polishing of the semiconductor wafer, the polishing table is rotated in a second direction while the conditioner is still in contact with polishing pad. Rotating the polishing pad in a second direction dislodges the polishing debris clogging the roughened surface of the conditioner and redistributes CMP slurry. The roughened surface of the pad conditioner is refreshed allowing more effective conditioning of the polishing pad. Pad life is prolonged, polishing is stabilized, and the polish cycle time is reduced.

An upper electrode is formed on one surface of a semiconductor multilayer structure including a light emitting layer. An interface electrode is formed at a region of another surface of the semiconductor multilayer structure except a region right under the upper electrode. A center of the interface electrode coincides with a center of the upper electrode. At least a part of the interface electrode has a similar shape to a shape of an outer periphery of the upper electrode. A current blocking layer is formed at another region of another surface of the semiconductor multilayer structure except the region where the interface electrode is formed. A reflecting layer for reflecting a part of the light emitted from the light emitting layer is electrically connected to the interface electrode. A conductive supporting substrate is electrically connected to the semiconductor multilayer structure.

There is provided a thin film transistor having improved reliability. A gate electrode includes a first gate electrode having a taper portion and a second gate electrode with a width narrower than the first gate electrode. A semiconductor layer is doped with phosphorus of a low concentration through the first gate electrode. In the semiconductor layer, two kinds of n⁻-type impurity regions are formed between a channel formation region and n⁺-type impurity regions. Some of the n⁻-type impurity regions overlap with a gate electrode, and the other n⁻-type impurity regions do not overlap with the gate electrode. Since the two kinds of n⁻-type impurity regions are formed, an off current can be reduced, and deterioration of characteristics can be suppressed.

A vertical cavity surface emitting laser (VCSEL) device with improved power and beam characteristics. The VCSEL device contains one VCSEL or an array of VCSELs. Each VCSEL has a corresponding integrated microlens, and a heat sink is attached to the device side of the VCSEL device. The heat sink allows improved heat dissipation, and therefore provides improved power characteristics of the VCSEL device output laser beam. The microlens or microlens array allows easier and more compact focussing of the VCSEL device output laser beam. The VCSEL device can be used in a variety of optical systems, and its improved power and focusing characteristics provide a compact, low power, low cost laser system.

A solar cell includes a doped layer disposed on a first surface of a semiconductor substrate, a doped polysilicon layer disposed in a first region of a second surface of the semiconductor substrate, a doped area disposed in a second region of the second surface, and an insulating layer covering the doped polysilicon layer and the doped area. The insulating layer has openings exposing portions of the doped polysilicon layer and the doped layer, and the doped polysilicon layer and doped layer are respectively connected to a first electrode and a second electrode through the openings. The semiconductor substrate and the doped layer have a first doping type. One of the doped polysilicon layer and the doping area has a second doping type, and the other one of the doped polysilicon layer and the doping area has the first doping type which is opposite to the second doping type.

Disclosed is a porous electrode comprising a porous film (A) with through pores and an electrically conducting material selected from the group consisting of conductor and semiconductor, the porous film (A) having an average pore size d1 of from 0.02 to 3 μm and a porosity of from 40 to 90%, the electrically conducting material being filled in the through pores of the porous film (A). A dye-sensitized solar cell and an electric double layer capacitor including the porous electrode as a constituent are also disclosed.

A system for creating mask layout pattern data in order to create a number of desired features on a semiconductor wafer. Critical features and features that are adjacent to or abut critical features are formed as phase shifting regions on a mask. Larger, non-critical features can be formed as annular rim shifters and may include one or more filling phase shifting regions. Non-critical features that are not adjacent to critical features and/or sub-resolution features that are not desired to print on the wafer can be formed as opaque or partially transparent regions on the mask.

The present invention discloses a thin film transistor and a method of fabricating the same. The thin film transistor includes an insulating substrate; and a semiconductor layer, a gate insulating layer, a gate electrode, an interlayer insulator, and a source/drain electrode which are formed on the substrate, wherein the gate insulating layer is formed of a filtering oxide layer having a thickness of 1 to 20 Å.

The following problem associated with a semiconductor device of silicon or the like having low band gap is solved by temperature estimation using voltage drop in such a semiconductor device having low accuracy and this complicates a circuit for temperature detection suitable for practical use or a configuration for implementing a detection system. A power converter provided with an inverter circuit includes a semiconductor device whose band gap is larger than that of silicon and which has a range in which the temperature coefficient of voltage drop during conduction is positive. The power converter further includes a measurement condition setting circuit. This circuit adjusts the timing of the following measurement values used for temperature estimation at a device temperature estimation circuit to each other so that a measurement value of a voltage measurement circuit and a measurement value of a current measurement circuit become data obtained by measurement at the same time.

It is an object to provide a semiconductor device for high power application which has good properties. A means for solving the above-described problem is to form a transistor described below. The transistor includes a source electrode layer; an oxide semiconductor layer in contact with the source electrode layer; a drain electrode layer in contact with the oxide semiconductor layer; a gate electrode layer part of which overlaps with the source electrode layer, the drain electrode layer, and the oxide semiconductor layer; and a gate insulating layer in contact with an entire surface of the gate electrode layer.

A highly reliable semiconductor device is provided. A semiconductor device is manufactured at a high yield, so that high productivity is achieved. In a semiconductor device including a transistor in which a gate electrode layer, a gate insulating film, an oxide semiconductor film containing indium, and an insulating layer provided on and in contact with the oxide semiconductor film so as to overlap with the gate electrode layer are stacked and a source electrode layer and a drain electrode layer are provided in contact with the oxide semiconductor film and the insulating layer, the chlorine concentration and the indium concentration on a surface of the insulating layer are lower than or equal to 1×10¹⁹/cm³ and lower than or equal to 2×10¹⁹/cm³, respectively.

A semiconductor device includes at least three or more wiring layers stacked in an interlayer insulating film on a semiconductor substrate, a seal ring provided at the outer periphery of a chip region of the semiconductor substrate and a chip strength reinforcement provided in part of the chip region near the seal ring. The chip strength reinforcement is made of a plurality of dummy wiring structures and each of the plurality of dummy wiring structures is formed to extend across and within two or more of the wiring layers including one or none of the bottommost wiring layer and the topmost wiring layer using a via portion.

A semiconductor integrated circuit having a built-in PLL circuit which has two charge pump circuits for charging and discharging capacitive elements of a loop filter in response to signals generated by a phase comparator circuit. One of the two charge pump circuits has current sources which generate current values smaller than those generated by current sources of the other charge pump circuit. The loop filter has a first capacitive element connected to a charge/discharge node, and a second capacitive element connected to the charge/discharge node through a resistive element. The first capacitive element is charged and discharged by the one charge pump circuit, while the second capacitive element is charged and discharged by the other charge pump circuit. A charging current source of the one charge pump circuit operates simultaneously with a discharging current source of the other charge pump circuit, i.e., the charge pump circuits operate in opposite phase.

A non-volatile memory device including a memory string including a plurality of memory cells coupled in series. The non-volatile memory device includes the memory string including a first semiconductor layer and a second conductive layer with a memory gate insulation layer therebetween, a first selection transistor comprising a second semiconductor layer coupled with one end of the first semiconductor layer, a second selection transistor comprising a third semiconductor layer coupled with the other end of the first semiconductor layer, and a fourth semiconductor layer contacting the first semiconductor layer in a region where the second conductive layer is not disposed.

The invention provides a preparation method of a top gate metal oxide thin film transistor (TFT), belonging to the technical field of semiconductors. The method comprises the following steps: preparing a source/drain electrode; then preparing a metal oxide material; coating a photoresist on the surface of the metal oxide material and carrying out chemical mechanical polishing on the photoresist layer; processing the metal oxide which is not masked by the photoresist by annealing or plasmas; and finally stripping the photoresist and depositing a gate insulation layer material through magnetronsputtering and forming a gate through wet etching. The method has the following beneficial effects: reliable ohmic contact between the metal oxide thin film and the source/drain electrode can be formed by utilizing the characteristic that the metal oxide material can be converted into a conductor from a semiconductor after undergoing special processing.

The invention is based on a method for examining structures on a semiconductor substrate. The structures are imaged with X-radiation in an X-ray microscope. The wavelength of the X-radiation is established as a function of the thickness of the semiconductor substrate in such a way that both a suitable transmission of the X-radiation through the semiconductor substrate and a high-contrast image are obtained. As a result, the structures can be observed continuously with short exposure times, high resolution and even while they are in operation.

The present invention comprises a modular microwave source comprising a novel electromagnetic oscillator based on a modified Blumlein architecture with an integrated antenna. In one or more embodiments, the invention comprises a triplate Blumlein in which the plates are configured and arranged to act as a waveguide and antenna. In one or more embodiments, high-permittivity dielectric materials are disposed between the center plate and one or both of the top and bottom plates to increase the energy storage and lengthen the duration of a damped sinusoid output. In one or more embodiments, photo-conductive semiconductor switches are disposed between the center plate and one or both of the top and bottom plates to act as high-speed switches. In one or more embodiments, a plurality of the modular microwave sources of the invention are arranged in an array, creating a compact, tunable, high-power microwave source suitable for mobile applications.

Particle formation in semiconductor fabrication process chambers is reduced by preventing condensation on the door plates that seal off the process chambers. Particles can be formed in a process chamber when reactant gases condense on the relatively cool surfaces of a door plate. This particle formation is minimized by heating the door plate to a temperature high enough to prevent condensation before flowing reactant gases into the process chamber. The door plate can be heated using a heat source, e.g., a resistive heater, that is in direct contact with the door plate or the heat source can heat the door plate from a distance by radiative or inductive heating. In addition, the door plate can open to allow loading and unloading of a wafer load. As it passes flanges near the door plate, the wafer load can transfer heat to those flanges. To prevent overheating, the flange is provided with a coolant-containing channel having walls that are spaced from the flange by O-rings. The spacing of the channel walls to the flange can be varied to vary the amount of thermal contact and cooling achieved using the channels.

The invention discloses a power semiconductor device and a manufacturing method thereof. The power semiconductor device comprises a substrate, a core forming layer, a buffer layer, a channel layer, a barrier layer, a source electrode, a drain electrode, a grid electrode and a junction termination structure located on the barrier layer. The junction termination structure extends in the direction from the edge, close to one side of the drain electrode, of the grid electrode to the drain electrode. Due to the piezoelectric effect caused by lattice constant difference between the junction termination structure and the barrier layer under the junction termination structure, two-dimensional electronic gas at the position of the interface of the barrier layer and the channel layer is partially exhausted. The junction termination structure can effectively improve the electric field distribution of the barrier layer so as to improve the breakdown voltage of the device.

Measurement circuit components are included in an integrated circuit fabricated on a semiconductor substrate. These measurement circuits are connected to a voltage regulation circuit that provides the integrated circuit voltage source. These measurement circuits provide signals to control the voltage regulation circuit to adjust the voltage output to the integrated circuit based upon a measurement values obtained on the semiconductor device. These measurements include temperature and IR drop at locations on the semiconductor substrate, along with the frequency response of integrated circuit.