758results about "Solid-state devices" patented technology

Flip-flops in a monolithic three-dimensional (3D) integrated circuit (IC)(3DIC) and related method are disclosed. In one embodiment, a single clock source is provided for the 3DIC and distributed to elements within the 3DIC. Delay is provided to clock paths by selectively controllable flip-flops to help provide synchronous operation. In certain embodiments, 3D flip-flop are provided that include a master latch disposed in a first tier of a 3DIC. The master latch is configured to receive a flip-flop input and a clock input, the master latch configured to provide a master latch output. The 3D flip-flop also includes at least one slave latch disposed in at least one additional tier of the 3DIC, the at least one slave latch configured to provide a 3DIC flip-flop output. The 3D flip-flop also includes at least one monolithic intertier via (MIV) coupling the master latch output to an input of the slave latch.

A photonic crystal structure is formed in an n-type region of a III-nitride semiconductor structure including an active region sandwiched between an n-type region and a p-type region. A reflector is formed on a surface of the p-type region opposite the active region. In some embodiments, the growth substrate on which the n-type region, active region, and p-type region are grown is removed, in order to facilitate forming the photonic crystal in an an-type region of the device, and to facilitate forming the reflector on a surface of the p-type region underlying the photonic crystal. The photonic crystal and reflector form a resonant cavity, which may allow control of light emitted by the active region.

A lighting device comprising first, second and third groups of solid state light emitters, the first group emitting light having a dominant wavelength of 430 to 490 nm, the second group at 525 to 575 (in some devices 540 to 575 nm), the third group at 610 to 640 nm. In some devices, wavelength of light from emitters in first and second groups, and light from second and third groups, differs by at least 70 nm. Some devices emit light having CRI Ra of at least 70 when first, second and third groups of emitters are illuminated. Also, a lighting arrangement comprising first, second and third groups as above, in addition to a fourth emitter emitting light of dominant wavelength outside the ranges for the first, second and third groups, and not more than 10 nm different from a dominant wavelength of a color on an item to be illuminated.

An interposer for use in an external lead or land pattern semiconductor package. The interposer includes an interposer body which is molded from a dielectric material. The interposer body defines opposed top and bottom surfaces, an outer peripheral edge, and an inner peripheral edge. Embedded within the interposer body is a die pad which itself defines opposed top and bottom surfaces and a peripheral edge. The bottom surface of the die pad is exposed in and substantially flush with the bottom surface of the interposer body, with the inner peripheral edge of the interposer body and the top surface of the die pad collectively defining a cavity of the interposer. A plurality of electrically conductive interposer leads are embedded within the top surface of the interposer body and at least partially exposed therein. The interposer body forms a nonconductive barrier between each of the interposer leads and between the interposer leads and the die pad.

In semiconductor devices in which both NMOS devices and PMOS devices are used to perform in different modes such as analog and digital modes, stress engineering is selectively applied to particular devices depending on their required operational modes. That is, the appropriate mechanical stress, i.e., tensile or compressive, can be applied to and/or removed from devices, i.e., NMOS and/or PMOS devices, based not only on their conductivity type, i.e., n-type or p-type, but also on their intended operational application, for example, analog/digital, low-voltage/high-voltage, high-speed/low-speed, noise-sensitive/noise-insensitive, etc. The result is that performance of individual devices is optimized based on the mode in which they operate. For example, mechanical stress can be applied to devices that operate in high-speed digital settings, while devices that operate in analog or RF signal settings, in which electrical noise such as flicker noise that may be introduced by applied stress may degrade performance, have no stress applied.

A semiconductor device includes a semiconductor substrate including a main surface; a plurality of first interconnections formed in a capacitance forming region defined on the main surface and extending in a predetermined direction; a plurality of second interconnections each adjacent to the first interconnection located at an edge of the capacitance forming region, extending in the predetermined direction, and having a fixed potential; and an insulating layer formed on the main surface and filling in between each of the first interconnections and between the first interconnection and the second interconnection adjacent to each other. The first interconnections and the second interconnections are located at substantially equal intervals in a plane parallel to the main surface, and located to align in a direction substantially perpendicular to the predetermined direction.

The invention enhances a production yield of a display device (an electro-optical device). The invention provides a method of manufacturing an electro-optical device including a display region in which a plurality of basic pixels are arranged, each basic pixel including a plurality of color pixels. The method includes: forming on a first substrate lines to drive a plurality of electro-optical elements respectively constituting the color pixels, correspondingly to the arrangement of the basic pixels; forming on a second substrate, as a chip to be transferred to each basic pixel, a drive circuit to drive the plurality of electro-optical elements which constitutes the plurality of color pixels of the basic pixels to obtain a plurality of basic-pixel driving chips; and transferring step of transferring the respective basic-pixel driving chips from the second substrate onto the first substrate, and connecting the drive circuits to regions of the lines corresponding to the basic pixels.

A display apparatus including a light emitting diode part including a plurality of regularly arranged light emitting diodes, and a TFT panel part configured to drive the light emitting diode part. The light emitting diode part includes a transparent electrode, the light emitting diodes regularly disposed on a first surface of the transparent electrode and electrically connected to the transparent electrode, a plurality of first reflective electrodes disposed at sides of the light emitting diodes, surrounding the light emitting diodes, and electrically connected to the transparent electrode, and a plurality of second reflective electrodes electrically connected to the light emitting diodes, respectively, and reflecting light emitted from the light emitting diodes.

A white light illumination system may comprise: a phosphor package; a first radiation source for providing co-excitation radiation to the phosphor package, the source emitting in wavelengths ranging from about 250 nm to about 410 nm; and a second radiation source for providing co-excitation radiation to the phosphor package, the source emitting in wavelengths ranging from about 410 nm to about 540 nm; wherein the phosphor package is configured to emit photoluminescence in wavelengths ranging from about 440 nm to about 700 nm upon co-excitation from the first and second radiation sources, and wherein the phosphor package comprises at least one narrow band green phosphor with a photoluminescence peak with a full width at half maximum of less than 60 nm, and wherein the narrow band green phosphor is configured to emit photoluminescence in wavelengths ranging from about 500 nm to about 550 nm.

In the case where high speed differential signals are transmitted in differential transmission lines through via holes with open-stubs, signal waveforms are distorted due to impedance mismatch in the open-stubs of the via holes, thus causing jitter, which has become an issue of high speed signals. For differential transmission lines that pass through via holes with open-stubs, a degree of coupling of the lines is decreased while the differential characteristic impedance is made constant. Thereby, the effects of backward cross talk noise caused by the coupling can be minimized, and thus jitter can be suppressed.

An image pickup device is disclosed that has little deformation caused by thermal expansion of a transparent resin for sealing an image pickup element. The image pickup device includes an image pickup element having a light receiving surface, a micro-lens for condensing incident light to the image pickup element, a first transparent plate disposed on the light receiving surface of the image pickup element with the micro-lens in between, a transparent resin that seals the image pickup element and the first transparent plate, and a second transparent plate disposed on the transparent resin to face the first transparent plate.

An upper electrode is formed on one surface of a semiconductor multilayer structure including a light emitting layer. An interface electrode is formed at a region of another surface of the semiconductor multilayer structure except a region right under the upper electrode. A center of the interface electrode coincides with a center of the upper electrode. At least a part of the interface electrode has a similar shape to a shape of an outer periphery of the upper electrode. A current blocking layer is formed at another region of another surface of the semiconductor multilayer structure except the region where the interface electrode is formed. A reflecting layer for reflecting a part of the light emitted from the light emitting layer is electrically connected to the interface electrode. A conductive supporting substrate is electrically connected to the semiconductor multilayer structure.

A polymer resin composition, a method for forming a pattern using the polymer resin composition, and a method for fabricating a capacitor using the polymer resin composition are disclosed. The polymer resin composition includes about 75 to 93 percent by weight of a copolymer prepared from benzyl methacrylate, methacrylic acid, and hydroxyethyl methacrylate; about 1 to 7 percent by weight of a cross-linking agent; about 0.01 to 0.5 percent by weight of a thermal acid generator; about 0.01 to 1 percent by weight of a photoacid generator; about 0.00001 to 0.001 percent by weight of an organic base; and a solvent.

There is provided a thin film transistor having improved reliability. A gate electrode includes a first gate electrode having a taper portion and a second gate electrode with a width narrower than the first gate electrode. A semiconductor layer is doped with phosphorus of a low concentration through the first gate electrode. In the semiconductor layer, two kinds of n⁻-type impurity regions are formed between a channel formation region and n⁺-type impurity regions. Some of the n⁻-type impurity regions overlap with a gate electrode, and the other n⁻-type impurity regions do not overlap with the gate electrode. Since the two kinds of n⁻-type impurity regions are formed, an off current can be reduced, and deterioration of characteristics can be suppressed.

A technique of manufacturing a display device with high productivity is provided. In addition, a high-definition display device with high color purity is provided. By adjusting the optical path length between an electrode having a reflective property and a light-emitting layer by the central wavelength of a wavelength range of light passing through a color filter layer, the high-definition display device with high color purity is provided without performing selective deposition of light-emitting layers. In a light-emitting element, a plurality of light-emitting layers emitting light of different colors are stacked. The closer the light-emitting layer is positioned to the electrode having a reflective property, the shorter the wavelength of light emitted from the light-emitting layer is.

A semiconductor package has a printed circuit board, an integrated circuit chip on the printed circuit board with an exposed semiconductor die, and a rigid structure secured to the printed circuit board and enclosing the exposed semiconductor die. The exposed surface of the semiconductor die placed is in thermal contact with an inner surface of the rigid structure with a compressible material.

A multilayer wiring board capable of feeding sufficient electric power to a circuit element, such as an IC chip. In one embodiment of the present invention, a multilayer wiring board is comprised of: a core board; a build up layer disposed on an upper surface of the core board; a build up layer disposed on a lower surface of the core board; and a power supply structure embedded in a through hole penetrating the core board and the build up layers. The power supply structure is comprised of: a conductive metal rod made of copper as a main material; a conductive metal tube made of copper as a main material and provided coaxially with the conductive metal rod; and an insulating material filling a gap between the conductive metal rod and the conductive metal tube.

A nanowire switching device and method. The device has a nanowire structure comprising an elongated member having a cross-sectional area ranging from about 1 nanometers but less than about 500 nanometers, but can also be at other dimensions, which vary or are substantially constant or any combination of these. The device also has a first terminal coupled to a first portion of the nanowire structure; and a second terminal coupled to a second portion of the nanowire structure. The second portion of the nanowire structure is disposed spatially from the first portion of the nanowire structure. An active surface structure is coupled to the nanowire structure. The active surface structure extends from the first portion to the second portion along the elongated member.

The invention discloses an organic light emitting display panel and a manufacturing method. The organic light emitting display panel comprises a substrate base plate; a light emitting element layer, located on a substrate base plate and provided with a plurality of first grooves; and a packaging layer, located above the light emitting element layer and filled in the plurality of first grooves. According to the invention, the plurality of first grooves are arranged in the light emitting element layer so that the packaging layer packaged above the light emitting element layer is filled in the plurality of first grooves, that is, a pinning structure is formed between the packaging layer and the light emitting element layer, thereby enhancing the adhesion between the packaging layer and the light emitting element layer and avoiding the stripping between the packaging layer and the light emitting element layer in a bending process.