Flip-flops in a monolithic three-dimensional (3D) integrated circuit (IC) (3DIC) and related methods

a three-dimensional integrated circuit and integrated circuit technology, applied in the field of three-dimensional three-dimensional integrated circuits (ic) (3dics) and components, can solve the problems of unacceptably high clock skew, slow clock signal, and component miniaturization and power consumption within the circuitry

Active Publication Date: 2014-09-11
QUALCOMM INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

This patent describes different ways to operate a computer chip with multiple processors connected together through specific timing channels. One method involves using flippers instead of traditional logic circuits. By providing a single clock signal to each processor at one level, it can be controlled more efficiently. These flipper devices distribute them over different levels of the chip, allowing for better synchronization between processing units.

Problems solved by technology

The technical problem addressed in this patent is how to reduce the size of electronic devices while still maintaining their functionality. Specifically, the desire to integrate smaller components into larger systems requires clock signals to be routed efficiently without increasing power consumption. However, conventional methods like placing them closer together can lead to clock skews and power consumption. Therefore, the goal is to develop new solutions to minimizing clock skewing and power consumption.

Method used

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  • Flip-flops in a monolithic three-dimensional (3D) integrated circuit (IC) (3DIC) and related methods
  • Flip-flops in a monolithic three-dimensional (3D) integrated circuit (IC) (3DIC) and related methods
  • Flip-flops in a monolithic three-dimensional (3D) integrated circuit (IC) (3DIC) and related methods

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Embodiment Construction

[0022]With reference now to the drawing figures, several exemplary embodiments of the present disclosure are described. The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments.

[0023]Embodiments disclosed in the detailed description include flip-flops in a monolithic three-dimensional (3D) integrated circuit (IC) (3DIC) and related methods. A single clock source is provided for the 3DIC and distributed to elements within the 3DIC. Delay is provided to clock paths by selectively controllable flip-flops to help provide synchronous operation. The flip-flops are spread across the tiers of the 3DIC such that part of the flip-flop is on a first tier and a second part of the flip-flop is on a second tier.

[0024]Before addressing the 3D flip-flop of the present disclosure, a brief overview of conventional flip-flops is provi

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Abstract

Flip-flops in a monolithic three-dimensional (3D) integrated circuit (IC)(3DIC) and related method are disclosed. In one embodiment, a single clock source is provided for the 3DIC and distributed to elements within the 3DIC. Delay is provided to clock paths by selectively controllable flip-flops to help provide synchronous operation. In certain embodiments, 3D flip-flop are provided that include a master latch disposed in a first tier of a 3DIC. The master latch is configured to receive a flip-flop input and a clock input, the master latch configured to provide a master latch output. The 3D flip-flop also includes at least one slave latch disposed in at least one additional tier of the 3DIC, the at least one slave latch configured to provide a 3DIC flip-flop output. The 3D flip-flop also includes at least one monolithic intertier via (MIV) coupling the master latch output to an input of the slave latch.

Description

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Claims

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Application Information

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Owner QUALCOMM INC
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