736results about "Semiconductor/solid-state device manufacturing" patented technology

The present invention provides a field effect transistor including an oxide film as a semiconductor layer, wherein the oxide film includes one of a source part and a drain part to which one of hydrogen and deuterium is added.

A wafer-supporting device for supporting a wafer thereon adapted to be installed in a semiconductor-processing apparatus includes: a base surface; and protrusions protruding from the base surface and having rounded tips for supporting a wafer thereon. The rounded tips are such that a reverse side of a wafer is supported entirely by the rounded tips by point contact. The protrusions are disposed substantially uniformly on an area of the base surface over which a wafer is placed, wherein the number (N) and the height (H [μm]) of the protrusions as determined in use satisfy the following inequities per area for a 300-mm wafer:

(−0.5N+40)≦H≦53; 5≦N<100.

A reactor for processing a substrate includes a first housing defining a processing chamber and supporting a light source and a second housing rotatably supported in the first housing and adapted to rotatably support the substrate in the processing chamber. A heater for heating the substrate is supported by the first housing and is enclosed in the second housing. The reactor further includes at least one gas injector for injecting at least one gas into the processing chamber onto a discrete area of the substrate and a photon density sensor extending into the first housing for measuring the temperature of the substrate. The photon density sensor is adapted to move between a first position wherein the photon density sensor is directed to the light source and a second position wherein the photon density sensor is positioned for directing toward the substrate. Preferably, the communication cables comprise optical communication cables, for example sapphire or quartz communication cables. A method of processing a semiconductor substrate includes supporting the substrate in a sealed processing chamber. The substrate is rotated and heated in the processing chamber in which at least one reactant gas is injected. A photon density sensor for measuring the temperature of the substrate is positioned in the processing chamber and is first directed to a light, which is provided in the chamber for measuring the incident photon density from the light and then repositioned to direct the photon density sensor to the substrate to measure the reflection of the light off the substrate. The incident photon density is compared to the reflected light to calculate the substrate temperature.

Flip-flops in a monolithic three-dimensional (3D) integrated circuit (IC)(3DIC) and related method are disclosed. In one embodiment, a single clock source is provided for the 3DIC and distributed to elements within the 3DIC. Delay is provided to clock paths by selectively controllable flip-flops to help provide synchronous operation. In certain embodiments, 3D flip-flop are provided that include a master latch disposed in a first tier of a 3DIC. The master latch is configured to receive a flip-flop input and a clock input, the master latch configured to provide a master latch output. The 3D flip-flop also includes at least one slave latch disposed in at least one additional tier of the 3DIC, the at least one slave latch configured to provide a 3DIC flip-flop output. The 3D flip-flop also includes at least one monolithic intertier via (MIV) coupling the master latch output to an input of the slave latch.

A method for reforming an amorphous carbon film as part of a deposition process thereof, includes process of: (i) depositing an amorphous carbon film on a substrate in a reaction space until a thickness of the amorphous carbon film reaches a predetermined thickness, and then stopping the deposition process; and (ii) exposing the amorphous carbon film to an Ar and/or He plasma in an atmosphere substantially devoid of hydrogen, oxygen, and nitrogen.

Embodiments of the present invention generally relate to a clamshell and small volume chamber with a fixed substrate support. One embodiment of a processing chamber includes a fixed substrate support having a substrate receiving surface, a pumping ring disposed around a perimeter of the substrate receiving surface, and a gas distribution assembly disposed over the fixed substrate support. The pumping ring forms at least a portion of a pumping channel and has one or more apertures formed therethrough. The chamber may further include a gas-flow diffuser disposed radially inward of the apertures of the pumping ring. Another embodiment of a processing chamber includes a first assembly comprising a fixed substrate support and a second assembly comprising a gas distribution assembly. The first assembly includes a first assembly body that is shaped and sized so that at least a portion of the first assembly body is below the substrate receiving surface of the substrate support. A hinge assembly couples the first assembly and the second assembly. The first assembly and the second assembly can be selectively positioned between an open position and a closed position.

In semiconductor devices in which both NMOS devices and PMOS devices are used to perform in different modes such as analog and digital modes, stress engineering is selectively applied to particular devices depending on their required operational modes. That is, the appropriate mechanical stress, i.e., tensile or compressive, can be applied to and/or removed from devices, i.e., NMOS and/or PMOS devices, based not only on their conductivity type, i.e., n-type or p-type, but also on their intended operational application, for example, analog/digital, low-voltage/high-voltage, high-speed/low-speed, noise-sensitive/noise-insensitive, etc. The result is that performance of individual devices is optimized based on the mode in which they operate. For example, mechanical stress can be applied to devices that operate in high-speed digital settings, while devices that operate in analog or RF signal settings, in which electrical noise such as flicker noise that may be introduced by applied stress may degrade performance, have no stress applied.

A semiconductor device includes a semiconductor substrate including a main surface; a plurality of first interconnections formed in a capacitance forming region defined on the main surface and extending in a predetermined direction; a plurality of second interconnections each adjacent to the first interconnection located at an edge of the capacitance forming region, extending in the predetermined direction, and having a fixed potential; and an insulating layer formed on the main surface and filling in between each of the first interconnections and between the first interconnection and the second interconnection adjacent to each other. The first interconnections and the second interconnections are located at substantially equal intervals in a plane parallel to the main surface, and located to align in a direction substantially perpendicular to the predetermined direction.

The invention enhances a production yield of a display device (an electro-optical device). The invention provides a method of manufacturing an electro-optical device including a display region in which a plurality of basic pixels are arranged, each basic pixel including a plurality of color pixels. The method includes: forming on a first substrate lines to drive a plurality of electro-optical elements respectively constituting the color pixels, correspondingly to the arrangement of the basic pixels; forming on a second substrate, as a chip to be transferred to each basic pixel, a drive circuit to drive the plurality of electro-optical elements which constitutes the plurality of color pixels of the basic pixels to obtain a plurality of basic-pixel driving chips; and transferring step of transferring the respective basic-pixel driving chips from the second substrate onto the first substrate, and connecting the drive circuits to regions of the lines corresponding to the basic pixels.

An image pickup device is disclosed that has little deformation caused by thermal expansion of a transparent resin for sealing an image pickup element. The image pickup device includes an image pickup element having a light receiving surface, a micro-lens for condensing incident light to the image pickup element, a first transparent plate disposed on the light receiving surface of the image pickup element with the micro-lens in between, a transparent resin that seals the image pickup element and the first transparent plate, and a second transparent plate disposed on the transparent resin to face the first transparent plate.

A polymer resin composition, a method for forming a pattern using the polymer resin composition, and a method for fabricating a capacitor using the polymer resin composition are disclosed. The polymer resin composition includes about 75 to 93 percent by weight of a copolymer prepared from benzyl methacrylate, methacrylic acid, and hydroxyethyl methacrylate; about 1 to 7 percent by weight of a cross-linking agent; about 0.01 to 0.5 percent by weight of a thermal acid generator; about 0.01 to 1 percent by weight of a photoacid generator; about 0.00001 to 0.001 percent by weight of an organic base; and a solvent.

There is provided a thin film transistor having improved reliability. A gate electrode includes a first gate electrode having a taper portion and a second gate electrode with a width narrower than the first gate electrode. A semiconductor layer is doped with phosphorus of a low concentration through the first gate electrode. In the semiconductor layer, two kinds of n⁻-type impurity regions are formed between a channel formation region and n⁺-type impurity regions. Some of the n⁻-type impurity regions overlap with a gate electrode, and the other n⁻-type impurity regions do not overlap with the gate electrode. Since the two kinds of n⁻-type impurity regions are formed, an off current can be reduced, and deterioration of characteristics can be suppressed.

A supported graphene device comprises at least one graphene feature of 1 to about 10 graphene layers having a predetermined shape and pattern, with at least a portion of each graphene feature being supported on a substrate. In some embodiments the device comprises graphene features supported on crystalline semiconductor substrate, such as silicon or germanium. The graphene features on a crystalline semiconductor substrate can be fabricated by forming an amorphous carbon doped semiconductor on the crystalline semiconductor substrate and then epitaxially crystallizing the amorphous semiconductor with carbon migration to the surface to form a graphene feature of one or more graphene layers. The epitaxy can be promoted by heating the device or by irradiation with a laser. Methods for fabricating graphene on a variety of substrates, over large areas with controlled thicknesses employ ion implantation or other doping techniques followed by pulsed laser annealing or other annealing techniques that result in solid phase regrowth are presented.

The present invention describes a transistor based on a Hetero junction FET structure, where the metal gate has been replaced by a stack formed by a highly doped compound semiconductor and an insulating layer in order to achieve enhancement mode operation and at the same time drastically reduce the gate current leakage. The combination of the insulating layer with a highly doped semiconductor allows the tuning of the threshold voltage of the device at the desired value by simply changing the composition of the semiconductor layer forming the gate region and/or its doping allowing a higher degree of freedom. In one of the embodiment, a back-barrier layer and a heavily doped threshold tuning layer are used to suppress Short Channel Effect phenomena and to adjust the threshold voltage of the device at the desired value. The present invention can be realized both with polar and non-polar (or semi-polar) materials.

A self-aligned gate cap dielectric can be employed to form a self-aligned contact to a diffusion region, while preventing electrical short with a gate conductor due to overlay variations. In one embodiment, an electroplatable or electrolessly platable metal is selectively deposited on conductive materials in a gate electrode, while the metal is not deposited on dielectric surfaces. The metal portion on top of the gate electrode is converted into a gate cap dielectric including the metal and oxygen. In another embodiment, a self-assembling monolayer is formed on dielectric surfaces, while exposing metallic top surfaces of a gate electrode. A gate cap dielectric including a dielectric oxide is formed on areas not covered by the self-assembling monolayer. The gate cap dielectric functions as an etch-stop structure during formation of a via hole, so that electrical shorting between a contact via structure formed therein and the gate electrode is avoided.

The invention discloses an organic light emitting display panel and a manufacturing method. The organic light emitting display panel comprises a substrate base plate; a light emitting element layer, located on a substrate base plate and provided with a plurality of first grooves; and a packaging layer, located above the light emitting element layer and filled in the plurality of first grooves. According to the invention, the plurality of first grooves are arranged in the light emitting element layer so that the packaging layer packaged above the light emitting element layer is filled in the plurality of first grooves, that is, a pinning structure is formed between the packaging layer and the light emitting element layer, thereby enhancing the adhesion between the packaging layer and the light emitting element layer and avoiding the stripping between the packaging layer and the light emitting element layer in a bending process.

A solar cell includes a doped layer disposed on a first surface of a semiconductor substrate, a doped polysilicon layer disposed in a first region of a second surface of the semiconductor substrate, a doped area disposed in a second region of the second surface, and an insulating layer covering the doped polysilicon layer and the doped area. The insulating layer has openings exposing portions of the doped polysilicon layer and the doped layer, and the doped polysilicon layer and doped layer are respectively connected to a first electrode and a second electrode through the openings. The semiconductor substrate and the doped layer have a first doping type. One of the doped polysilicon layer and the doping area has a second doping type, and the other one of the doped polysilicon layer and the doping area has the first doping type which is opposite to the second doping type.

An exposure apparatus, which exposes a pattern on an original onto a substrate while a liquid fills a gap between a projection optical system and the substrate, includes a liquid holding plate which sets the substrate held on a substrate stage and the peripheral area around the peripheral portion of the substrate to form substantially the same surface to hold the liquid on the peripheral portion of the substrate. The liquid holding plate includes an inner member formed in the peripheral area of the peripheral portion of the substrate and holds the liquid on the peripheral portion of the substrate, an outer member formed on the peripheral portion of the inner member and attaching to the substrate stage, and a connection member which connects the inner member to the outer member.

Different types of thin film transistors are disposed on the same flexible substrate and an organic light emitting display using the same includes a display area and a non-display area; a first buffer layer over an entire surface of the flexible substrate; a driving transistor on the buffer layer in the display area, the driving transistor including a polycrystalline silicon (LIPS) layer, a first gate electrode, a first source electrode, and a first drain electrode; a capacitor electrode on the first source electrode of the driving transistor and forming a storage capacitor together with the first source electrode; a switching transistor in the display area to be spaced apart from the driving transistor; and a dummy electrode on the switching transistor, the dummy electrode formed of the same material as the capacitor electrode, and disposed on the same plane as the capacitor.