49 results about "Device material" patented technology

In semiconductor devices in which both NMOS devices and PMOS devices are used to perform in different modes such as analog and digital modes, stress engineering is selectively applied to particular devices depending on their required operational modes. That is, the appropriate mechanical stress, i.e., tensile or compressive, can be applied to and/or removed from devices, i.e., NMOS and/or PMOS devices, based not only on their conductivity type, i.e., n-type or p-type, but also on their intended operational application, for example, analog/digital, low-voltage/high-voltage, high-speed/low-speed, noise-sensitive/noise-insensitive, etc. The result is that performance of individual devices is optimized based on the mode in which they operate. For example, mechanical stress can be applied to devices that operate in high-speed digital settings, while devices that operate in analog or RF signal settings, in which electrical noise such as flicker noise that may be introduced by applied stress may degrade performance, have no stress applied.

A semiconductor device includes a semiconductor substrate including a main surface; a plurality of first interconnections formed in a capacitance forming region defined on the main surface and extending in a predetermined direction; a plurality of second interconnections each adjacent to the first interconnection located at an edge of the capacitance forming region, extending in the predetermined direction, and having a fixed potential; and an insulating layer formed on the main surface and filling in between each of the first interconnections and between the first interconnection and the second interconnection adjacent to each other. The first interconnections and the second interconnections are located at substantially equal intervals in a plane parallel to the main surface, and located to align in a direction substantially perpendicular to the predetermined direction.

There is provided a thin film transistor having improved reliability. A gate electrode includes a first gate electrode having a taper portion and a second gate electrode with a width narrower than the first gate electrode. A semiconductor layer is doped with phosphorus of a low concentration through the first gate electrode. In the semiconductor layer, two kinds of n⁻-type impurity regions are formed between a channel formation region and n⁺-type impurity regions. Some of the n⁻-type impurity regions overlap with a gate electrode, and the other n⁻-type impurity regions do not overlap with the gate electrode. Since the two kinds of n⁻-type impurity regions are formed, an off current can be reduced, and deterioration of characteristics can be suppressed.

A semiconductor device includes at least three or more wiring layers stacked in an interlayer insulating film on a semiconductor substrate, a seal ring provided at the outer periphery of a chip region of the semiconductor substrate and a chip strength reinforcement provided in part of the chip region near the seal ring. The chip strength reinforcement is made of a plurality of dummy wiring structures and each of the plurality of dummy wiring structures is formed to extend across and within two or more of the wiring layers including one or none of the bottommost wiring layer and the topmost wiring layer using a via portion.

To provide a method for manufacturing a large semiconductor device which easily operates normally and has excellent current characteristics. A first single-crystal semiconductor layer is provided over an insulating substrate. Then, the first single-crystal semiconductor layer is processed into an island shape. After that, a second single-crystal semiconductor layer is provided over the insulating substrate so as to overlap with part of a region where the first single-crystal semiconductor layer is provided. After that, the second single-crystal semiconductor layer is processed into an island shape. Thus, defects at joint portions in the case of providing the single-crystal semiconductor layers can be reduced.

Techniques for data storage are provided. In one aspect, a method for writing one or more magnetic memory cells comprises the following steps. Data is written to one or more of the magnetic memory cells. It is detected whether there are any errors in the data written to the one or more magnetic memory cells. The data is rewritten to each of the one or more previously written magnetic memory cells in which an error is detected.

A method for manufacturing a semiconductor device having a movable portion includes the steps of: forming a trench on a semiconductor layer so that the trench reaches an insulation layer; and forming a movable portion by etching a sidewall of the trench so that the semiconductor layer is separated from the insulation layer. The steps of forming the trench and forming the movable portion are performed by a reactive ion etching method. The insulation layer disposed on the bottom of the trench is prevented from charging positively in the step of forming the trench. The insulation layer disposed on the bottom of the trench is charged positively in the step of forming the movable portion.

In a method of forming a metal interconnect of a semiconductor device using a damascene process, an etch stop layer and an insulating layer are successively formed on a semiconductor substrate, into which a conductive pattern is filled. Next, the etch stop layer and the insulating layer are patterned so that an opening for exposing the etch stop layer is formed. Subsequently, a first diffusion barrier layer is formed along inner surfaces of the opening. The first diffusion barrier layer on a bottom surface of the opening and the etch stop layer are removed through an etch process using a sputtering method. Finally, a conductive material which is electrically connected to the conductive pattern is filled into the opening.

A source-drain voltage of one of two transistors connected in series becomes quite small in a set operation (write signal), thus the set operation is performed to the other transistor. In an output operation, two transistors operate as a multi-gate transistor, therefore, a current value can be small in the output operation. In other words, a current can be large in the set operation. Therefore, the set operation can be performed rapidly without being easily influenced by an intersection capacitance and a wiring resistance which are parasitic on a wiring and the like. Further, an influence of variations between adjacent ones can be small as one same transistor is used in the set operation and the output operation.

Method of forming fine patterns and methods of fabricating semiconductor devices by which a photoresist (PR) pattern may be transferred to a medium material layer with a small thickness and a high etch selectivity with respect to a hard mask to form a medium pattern and the hard mask may be formed using the medium pattern. According to the methods, the PR pattern may have a low aspect ratio so that a pattern can be transferred using a PR layer with a small thickness without collapsing the PR pattern.

A semiconductor device includes a compound semiconductor substrate, a channel layer provided on the compound semiconductor substrate, a buried layer provided on the channel layer, a first recess formed in the buried layer in an E-mode region, a second recess formed in the first recess in the E-mode region and another second recess formed in the buried layer in a D-mode region, and a gate electrode provided in the second recess in the E-mode region and another gate electrode provided in the second recess in the D-mode region, and a distance between a surface of the buried layer and a bottom of the second recess in the E-mode region is shorter than another distance between another surface of the buried layer and a bottom of said another second recess in the D-mode region.

Disclosed is an electrostatic discharge (ESD) protection circuit. The ESD protection circuit may include a silicon controller rectifier (SCR) which may be triggered via at least one of its first trigger gate or second trigger gate. The ESD protection circuit may further include a highly doped region coupled to either the anode or cathode of the SCR, wherein the highly doped region may provide additional carriers to facilitate triggering of the SCR during an ESD event, whereby the SCR may be triggered more quickly.

A nitride semiconductor power device includes an AlGaN multilayer, which has changeable Al composition along a depositing direction, and Si_xNy layer, so as to minimize an increase in a leakage current and a decrease in a breakdown voltage, which are caused while fabricating a heterojunction type HFET device. A semiconductor device includes a buffer layer, an AlGaN multilayer formed on the buffer layer, a GaN channel layer formed on the AlGaN multilayer, and an AlGaN barrier layer formed on the AlGaN multilayer, wherein aluminum (Al) composition of the AlGaN multilayer changes along a direction that the AlGaN multilayer is deposited.

The invention provides a cascode transistor circuit with a depletion mode transistor and a switching device. A gate bias circuit is connected between the gate of the depletion mode transistor and the low power line. The gate bias circuit is adapted to compensate the forward voltage of a diode function of the switching device. The depletion mode transistor and the gate bias circuit are formed as part of an integrated circuit.

In a method for manufacturing a semiconductor device having an alignment mark, a buffer layer is formed on a substrate. A trench is formed at an isolation region of the substrate. The trench is filled with an insulating layer. An alignment groove is formed on the insulating layer in a scribe lane region of the substrate. The buffer layer is removed to form an alignment pattern. An alignment mark includes the alignment pattern and the alignment groove. Therefore, the alignment pattern may be not attacked by solutions in a successive cleaning process such that the alignment mark may be not damaged and maintains its original shape.

A semiconductor device packaged in a plastic package, the semiconductor device being provided with a semiconductor device chip further provided with plural leads arranged along the top surface of the semiconductor device chip and a plastic mold covering the semiconductor device chip, wherein the plastic mold is limited to the top surface of the semiconductor device chip and the shape of the leads is J-shape or U-shape, whereby the connection between the leads and a printed board is made strong, resulting enhanced reliability of the semiconductor device from the electrical and mechanical viewpoints.

In performing exposure for forming patterns being fine as well as having great density difference, adequate corrections are to be enabled for suppressing the influence from peripheries of these patterns to be a minimum and for suppressing the dimension variation within the plane of semiconductor substrate or among semiconductor substrates to a minimum. So-called lower-layer corrections are executed, in order to suppress the three-dimensional influence, namely the influence of the film-thickness distribution of a lower-layer structure body lying under a subject film to be processed with a resist. A pattern-correcting portion adjusts the amount of exposure such that it cancels the in-plane film-thickness distribution of the lower-layer structure body in respective exposure regions.

A thermally conductive sheet of the present invention includes a thermosetting resin (A) and an inorganic filler material (B) that is dispersed in the thermosetting resin (A). In the thermally conductive sheet of the present invention, at a frequency of 1 kHz and at a temperature of 100° C. to 175° C., the maximum value of a dielectric loss factor of a cured product of the thermally conductive sheet is less than or equal to 0.030, and a change in relative dielectric constant of the cured product of the thermally conductive sheet is less than or equal to 0.10.

The invention discloses a wafer-level packaging method of a semiconductor device and belongs to the technical field of semiconductor packaging. The method comprises the steps that a silicon wafer is taken; arraying of an insulation layer, a conducting electrode, a silicon through hole, a re-wiring metal layer and the like is completed on the silicon wafer through a wafer-level silicon substrate adapter plate, and an inversion zone is reserved for an LED chip; the LED chip is arranged inversely to the inversion zone; a light transmission layer covering the LED chip is formed, and the surface of the light transmission layer is subjected to roughening; and the silicon wafer obtained after packaging is cut into packaging bodies of single semiconductor devices. According to the wafer-level packaging method of the packaging structure of the semiconductor device, the wafer-level silicon substrate adapter plate technology and the surface roughening technology are used for forming the packaging structure of chips with the same size, size is small, a heat resistance value is low, cost is low, and brightness is high.

The invention relates to a high-reliability SGT device with an up-down structure. The semiconductor device comprises a semiconductor substrate with a first conductive type and a cellular region prepared in a drift region of the semiconductor substrate, and cells in the cellular region adopt groove structures; on the overlook plane of the SGT device, a cell in a cell region comprises a square-ring-shaped cell peripheral groove and a cell center groove located in the center region of the inner ring of the cell peripheral groove; a second conduction type base region is arranged on the outer ring of the cell center groove, the second conduction type base region is located above the corresponding groove bottoms of the cell center groove and the cell peripheral groove in the drift region, and the second conduction type base region is in contact with the outer side wall of the cell center groove and the outer side wall of the inner ring of the cell peripheral groove; warping caused by different stress in the transverse direction and the longitudinal direction can be effectively reduced, and voltage withstanding reliability caused by voltage withstanding BV difference of the drift region can be effectively reduced.

The invention discloses a semiconductor device with a Schottky metal junction and a manufacturing method thereof. The semiconductor device comprises a substrate and an epitaxial layer formed on the surface of the substrate, a plurality of grooves are formed in the epitaxial layer, and each groove is filled with polycrystalline silicon. A gate oxide layer is formed between the polycrystalline silicon and the trench, a first metal layer is formed on the upper surface of the polycrystalline silicon, a second metal layer is formed on the upper surface, adjacent to the polycrystalline silicon, of the epitaxial layer, the first metal layer is further formed on the upper surface of the epitaxial layer, and a Schottky barrier formed by the second metal layer and the epitaxial layer is different from a Schottky barrier formed by the first metal layer and the epitaxial layer in size. According to the invention, two different barrier metals are used as Schottky contacts, when the device is reversely blocked, the Schottky barrier current is reduced by using the electric field shielding effect of the high-barrier Schottky metal on the low-barrier Schottky metal, and when the device is positively conducted, the device has relatively low conduction voltage drop due to the low-barrier Schottky metal.

A 3D memory device, the device including: a first vertical pillar, the first vertical pillar includes a transistor source; a second vertical pillar, the second vertical pillar includes the transistor drain, where the first vertical pillar and the second vertical pillar each functions as a source or functions as a drain for a plurality of overlaying horizontally-oriented memory transistors, where at least of one of the plurality of overlaying horizontally-oriented memory transistors is disposed between the first vertical pillar and the second vertical pillar, where the plurality of overlaying horizontally-oriented memory transistors are self-aligned being formed following a same lithography step, and where the first vertical pillar includes metal.