47results about "Read-only memories" patented technology

The method of operating the nonvolatile memory device may include performing a read operation on a first address region, comparing a read time of the first address region with a reference time, and storing read data from the read from the first address region in a second address region based on the comparison result.

A method of operation of a storage control system includes: determining a bit error rate of a page; calculating a slope based on the bit error rate; and adjusting a threshold voltage for the page based on the slope for reading a memory device.

Integrated circuit memory devices include an array of nonvolatile N-bit memory cells, where N is an integer greater than one. Control circuitry is also provided to reliably read data from the N-bit memory cells. This control circuitry, which is electrically coupled to the array, is configured to determine, among other things, a value of at least one bit of data stored in a selected N-bit memory cell in the array. This is done by decoding at least one hard data value and a plurality of soft data values (e.g., 6 data values) read from the selected N-bit memory cell using a corresponding plurality of unequal read voltages applied to the selected N-bit memory cell during a read operation.

A phase change memory device includes a memory cell having a phase change material, a write driver which supplies a step-down set current to the memory cell, where the step-down set current includes a plurality of successive steps of decreasing current magnitude, and a set program control circuit which controls a duration of the step-down set current supplied by the write driver.

A process and a memory architecture is based on “vertical” pages, and support byte by byte erasure. A byte within a “vertical” page is erased, and then other bytes within the “vertical” page sharing bit lines with the erased byte, are subjected to a program verify operation after exposure to the stress caused by the erase process. The other bytes in the page are re-programmed to recover the data if they fail verify. Therefore, byte erase is executed without the erase/re-program cycling, and only memory cells within the same vertical page as the erased byte, which suffer stress from the erase potentials on the shared bit lines sufficient to shift their thresholds out of range, are re-programmed.

A method for reading a NAND flash memory device is provided. The NAND flash memory device includes a first bit line that is selected and a second bit line that is not selected. Each bit line is connected to a cell string including a string selection transistor, a plurality of memory cell transistors, and a source selection transistor connected in series. In the method, first, the first bit line is precharged while power supply voltage is applied to the second bit line. The string selection transistors are turned on and a read voltage is applied to a selected memory cell while a pass voltage is applied to unselected memory cells. The state of the selected memory cell transistor is detected according to whether or not charge precharged on the first bit line has been discharged.

A method, system and memory controller are provided for implementing ECC (Error Correction Codes) control to provide enhanced endurance and data retention of flash memories. The memory controller includes a VT (threshold voltage) monitor to determine VT degradation of cells and blocks; the VT monitor configured to store information about the determined VT degradation; a first ECC engine having a first level of ECC capability; a second ECC engine having a second level of ECC capability, the second level higher than the first level, the second ECC engine having a longer latency than the first ECC engine; a logic to issue a read request to a particular cell/block, and, using the determined VT degradation, use the first ECC engine if the determined VT degradation is less than a threshold and to use the second ECC engine if the determined VT degradation is above the threshold.

An INVSRC node and a SAREF node are previously precharged. After a potential on a bit line is reset, the bit line (BLS node) is precharged. In this event, a clamp MOS transistor in a sense amplifier is in ON state, and an SA node is also precharged simultaneously. A precharge level is set to a value lower than a threshold voltage of an inverter. Subsequently, when SAEN transitions to “H,” a sense operation is performed. For reading data “0,” the SA node is rapidly increased to Vdd. For reading data “1,” the SA node slowly approaches to Vss. A change in the potential at the SA node is detected by the inverter.

A system has a reduced sensitivity to Single Event Upset and/or Single Event Transient(s) compared to traditional logic devices. In a particular embodiment, the system includes an input, a logic block, a bias stage, a state machine, and an output. The logic block is coupled to the input. The logic block is for implementing a logic function, receiving a data set via the input, and generating a result f by applying the data set to the logic function. The bias stage is coupled to the logic block. The bias stage is for receiving the result from the logic block and presenting it to the state machine. The state machine is coupled to the bias stage. The state machine is for receiving, via the bias stage, the result generated by the logic block. The state machine is configured to retain a state value for the system. The state value is typically based on the result generated by the logic block. The output is coupled to the state machine. The output is for providing the value stored by the state machine. Some embodiments of the invention produce dual rail outputs Q and Q′. The logic block typically contains combinational logic and is similar, in size and transistor configuration, to a conventional CMOS combinational logic design. However, only a very small portion of the circuits of these embodiments, is sensitive to Single Event Upset and/or Single Event Transients.

A flash memory device including: a memory cell array; a signal generator inputting a first data fetch signal and outputting a second data fetch signal; and an output buffer circuit configured to output data from the memory cell array in sync with rising and falling edges of the second data fetch signal, wherein second data fetch signal is output along with data output from the output buffer circuit.

A semiconductor integrated circuit device including a dynamic random access memory (DRAM) unit having improved signal-to-noise ratio, reduced bit line capacitance, and reduced area is provided. The DRAM unit includes a plurality of bit line pairs, each bit line pair including a first metal conductor and a second metal conductor. Each bit line pair includes a reference bit line and a sense bit line. Each bit line pair may be configured such that the reference bit line and the sense bit line are longitudinally oriented with respect to each other. Alternatively, each bit line pair is configured such that the first metal conductor and the second metal conductor are symmetrically twisted about each other in at least one location. The lateral spacing between a cell plate and a transistor gate is minimized, resulting in reduced overall area.

A nonvolatile memory system includes a nonvolatile memory device including a plurality of memory cells; and a memory controller suitable for recovering normal data based on a recovery read level interval when an error occurs in the normal data read from the memory cells by using a reference read level, wherein the memory controller generates N distribution measurement values by measuring distribution values of threshold voltage levels of the memory cells at N respective distribution read levels, which have a preset read level interval with the reference read level serving as a center, and determines the recovery read level interval through calculating variations of the N distribution measurement values by using a linear equation, where ‘N’ is a natural number equal to or larger than 2.

A non-volatile memory device and an operating method thereof are provided. The non-volatile memory device includes a memory unit including a plurality of memory blocks and a cam block, a peripheral circuit unit configured to program memory cells included in the plurality of memory blocks and the cam block or read programmed data, and a processor configured to control the peripheral circuit unit to measure an offset voltage by memory cell group in the plurality of memory blocks to set a read voltage during a test read operation and control the peripheral circuit unit to perform a read operation by memory cell group by using a new read voltage during a read operation.

A method for programming an MLC flash memory device minimizes interference between adjacent cells during a program operation, such that threshold voltage distribution becomes narrow and uniform. According to the method, an auxiliary program operation is performed on memory cells to be programmed, such that a majority of the memory cells have a positive threshold voltage. An LSB of a particular memory cell is programmed to a predetermined level, and data of the programmed LSB is sensed. An MSB of the particular memory cell is programmed to a predetermined level according to the sensed data of the LSB.

A control terminal section CON and an address terminal section ADDR of a test apparatus are respectively connected to those of a flash memory. A first to an (n−1) -th input and output terminal of the test apparatus are connected to data terminals of the flash memory. Further, an n-th and an (n+1)-th input and output terminal of the test apparatus are connected to a multifunctional terminal of the flash memory. The (n+1)-th input and output terminal is established as a dedicated terminal to receive data supplied to the test apparatus. The first to the n-th input and output terminal of the test apparatus are used to output the writing data to the flash memory, while the (n+1)-th input and output terminal is used to detect the completion signal output from the flash memory.

An exemplary sensing circuit for sensing the current drawn by a target memory cell comprises a first transistor connected across a first node and a second node, a load connected across the second node and a third node, and a voltage boosting circuit coupled to a supply voltage, wherein the voltage boosting circuit supplies a voltage at the third node which is greater than the supply voltage.

A data storage device including a flash memory, a temperature sensor, and a controller. The temperature sensor detects surrounding ambient temperature. The controller reads the temperature sensor to obtain a current temperature parameter at a predetermined time, compares a plurality of write temperatures of the blocks with the current temperature parameter one by one, and writes data stored in at least one first block of the blocks into at least one third block of the blocks, wherein the first block corresponds to at least one first write temperature of the write temperatures, and the difference between the first write temperature and the current temperature parameter is greater than a predetermined value.

A method includes determining groups of rows to erase together in order to minimize the margin loss associated with bake after a large number of program and erasure cycles. The method alternatively includes determining groups of rows to erase together to minimize the width of a resultant erase threshold voltage distribution, erasing the groups together, stopping erasure of a group when the group is erase verified and performing the step of erasing on those groups which were not previously erase verified.

An unbalanced plane management method, an associated data storage device and the controller thereof are provided. The unbalanced plane management method may include: setting an unbalanced plane number; selecting at least one plane with a plane count calculated by subtracting the unbalanced plane number from a maximum plane number, and recording at least one set of blocks of the at least one plane to a block skip table; according to block numbers as indexes, combining blocks of unselected planes into super blocks, wherein said super blocks respectively correspond to said block numbers; and recording total capacity of all super blocks and the unbalanced plane number, to generate a latest record of records of multiple types of storage capacity, for further setting storage capacity configuration of the data storage device, wherein said all super blocks include said super blocks.

The invention discloses a ROM and a layout thereof. The ROM comprises at least one MOS (Metal Oxide Semiconductor) tube, bit lines and word lines, wherein each MOS tube is corresponding to at least two bit lines, and based on the connection states of two or more bit lines and the MOS tube, the MOS tube can store more than two types of state information. Namely, under the premise of fixed storage area of the ROM, by increasing the number of bit line regions, programmable information of one MOS tube of the ROM is more than 1 bit, and correspondingly, the storage area of the 1 bit of information is reduced.

A non-volatile memory includes an array (30) of cells in rows and columns (311-316; 331-336),where the cells of each column (311-316; 331-336) are positioned within a respective isolated p-well region (301, 302, 303). Control gates of sequential memory cells in rows of the array (311, 321, 331; 316, 316, 336) are electrically coupled by common wordlines (3071, 3072 3076). Bitlines (3091, 3092, 3093) electrically couple drain or source regions of each memory cell in the respective columns (311-316; 331-336). The source lines (3051, 3052, 3053) and at least one memory cell in each column of the array (311-316; 331-336) are electrically coupled to the p-well region (301, 302, 303) corresponding to the column of the source line and cell. Each column of the array (30) is therefore located within an isolated well.

The invention relates to a booster circuit and method for improving the programming accuracy of an EEPROM. The booster circuit comprises a register, an MOS tube switch array, a reference source, a charge pump and the EEPROM. The booster circuit fully utilizes the characteristic that the data of the EEPROM memorizer can be saved for enough long time when a chip is powered down to specially mark out a small part of an EEPROM storage area as a special correction area. The booster circuit has the advantages that a common register is firstly used for adjusting the accuracy of the booster circuit in a chip testing mode, the EEPROM can perform normal programming and stores the data in the register in the EEPROM special correction area when an accurate booster circuit voltage value is obtained. The booster circuit occupies small chip area and is low in cost. In addition, the register in the circuit can be repeated scanned, the digit can be corrected to be higher, and the correction accuracy is high.

A non-volatile memory device includes a control circuit configured to perform a block erase operation including a block erase cycle and an erase verify cycle on a block of memory cells. The control circuit is configured to perform the erase verify cycle by storing a last verify address for each sector of the block of memory cells, verifying each memory cell in a sector starting from the last verify address for the sector until a memory cell has failed erase verification in that sector, storing the memory cell address of the failed memory cell as the last verify address for that sector, skipping the erase verification for the remaining memory cells in that sector, and continuing the erase verify cycle at a last verify address for the next sector.

An E-fuse array circuit includes a driving block arranged in a predetermined portion of a semiconductor substrate, a normal fuse array configured to one side of the driving block, and an auxiliary circuit part arranged in an other side of the driving block to a direction facing an arrangement direction of the normal fuse array.

A NAND memory device that includes a plurality of blocks, each block comprises a plurality of wordlines and an associated agent, and each wordline comprises a plurality of cells and a plurality of voltage levels and an associated agent, and each voltage level comprises an agent. A method of programming the NAND memory device includes receiving, by an agent at a given rank in the plurality of ranks, parameters from a higher rank agent in the hierarchy of ranks and a state from the memory device; determining, by the agent, an action from the parameters and the state; passing the action as parameters to a lower rank agent in the hierarchy of ranks; and updating the agent based on a reward output by the agent, wherein the reward measures a difference between the target voltage levels of the cells and the actual voltage levels programmed to the cells.