13 results about "Bit line" patented technology

A process and a memory architecture is based on “vertical” pages, and support byte by byte erasure. A byte within a “vertical” page is erased, and then other bytes within the “vertical” page sharing bit lines with the erased byte, are subjected to a program verify operation after exposure to the stress caused by the erase process. The other bytes in the page are re-programmed to recover the data if they fail verify. Therefore, byte erase is executed without the erase/re-program cycling, and only memory cells within the same vertical page as the erased byte, which suffer stress from the erase potentials on the shared bit lines sufficient to shift their thresholds out of range, are re-programmed.

A method for reading a NAND flash memory device is provided. The NAND flash memory device includes a first bit line that is selected and a second bit line that is not selected. Each bit line is connected to a cell string including a string selection transistor, a plurality of memory cell transistors, and a source selection transistor connected in series. In the method, first, the first bit line is precharged while power supply voltage is applied to the second bit line. The string selection transistors are turned on and a read voltage is applied to a selected memory cell while a pass voltage is applied to unselected memory cells. The state of the selected memory cell transistor is detected according to whether or not charge precharged on the first bit line has been discharged.

An INVSRC node and a SAREF node are previously precharged. After a potential on a bit line is reset, the bit line (BLS node) is precharged. In this event, a clamp MOS transistor in a sense amplifier is in ON state, and an SA node is also precharged simultaneously. A precharge level is set to a value lower than a threshold voltage of an inverter. Subsequently, when SAEN transitions to “H,” a sense operation is performed. For reading data “0,” the SA node is rapidly increased to Vdd. For reading data “1,” the SA node slowly approaches to Vss. A change in the potential at the SA node is detected by the inverter.

A semiconductor integrated circuit device including a dynamic random access memory (DRAM) unit having improved signal-to-noise ratio, reduced bit line capacitance, and reduced area is provided. The DRAM unit includes a plurality of bit line pairs, each bit line pair including a first metal conductor and a second metal conductor. Each bit line pair includes a reference bit line and a sense bit line. Each bit line pair may be configured such that the reference bit line and the sense bit line are longitudinally oriented with respect to each other. Alternatively, each bit line pair is configured such that the first metal conductor and the second metal conductor are symmetrically twisted about each other in at least one location. The lateral spacing between a cell plate and a transistor gate is minimized, resulting in reduced overall area.

A semiconductor structure with improved capacitance of bit lines includes a substrate, a stacked memory structure, a plurality of bit lines, a first stair contact structure, a first group of transistor structures and a first conductive line. The first stair contact structure is formed on the substrate and includes conductive planes and insulating planes stacked alternately. The conductive planes are separated from each other by the insulating planes for connecting the bit lines to the stacked memory structure by stairs. The first group of transistor structures is formed in a first bulk area where the bit lines pass through and then connect to the conductive planes. The first group of transistor structures has a first gate around the first bulk area. The first conductive line is connected to the first gate to control the voltage applied to the first gate.

A multi-port memory array according to some embodiments of the present invention includes a first complementary pair of bit lines of length L corresponding to a first port; a second complementary pair of bit lines of length L corresponding to a second port, wherein the first complementary pair of bit lines is interleaved with the second complementary pair of bit lines, and wherein the first complementary pair of bit lines is twisted at L/2 and the second complementary pair of bit lines is twisted at L/4 and 3L/4. The capacitive coupling between a bit line of the first complementary pair of bit lines and each of the bit lines of the second complementary pair of bit lines is therefore the same, resulting in an elimination of the effects of capacitive coupling.

The present invention proposes a static random-access memory device (SRAM). The static random-access memory device is composed of two P-channel gates of loading transistor, two N-channel gates of driving transistor and two N-channel gates of accessing transistor in a memory cell. A dummy gate is disposed adjacent to the N-channel gate of accessing transistor with a bit line node disposed therebetween, wherein the dummy gate is electrically connected to a ground voltage through a metal layer.

A semiconductor memory device for reading or writing data from or to a memory cell includes at least one cell array having a plurality of memory cells for outputting a stored data to one of a bit line and a bit line bar in response to inputted address and command; at least one reference cell array for outputting a reference signal to the other of the bit line and the bit line bar; a precharge block for precharging the bit line and the bit line bar as a ground; and a sense amplifying block for sensing and amplifying the data by using a core voltage for operating the semiconductor memory device and a high voltage having a higher voltage level than the core voltage.

A bit line resetting signal is supplied to the gate of an nMOS transistor (or a precharge circuit) which connects a bit line with a precharge voltage line. The high-level voltage of the bit line resetting signal is retained at a first voltage during the precharge operation after a refresh operation, and is retained at a second voltage higher than the first voltage during the precharge operation after an access operation. In the precharge operation after the refresh operation, therefore, the second voltage is not used so that the current consumption of the generating circuit of the second voltage is reduced. Thus, it is possible to reduce the current consumption (or the standby current) during the standby period for which the internal refresh requests continuously occur.

A memory apparatus may include a bit line sense-amplifier coupled to first and second bit lines; a first precharge unit suitable for coupling the first and second bit lines in response to a bit line equalization signal; a sense-amplifier power control unit suitable for providing a plurality of powers to the bit line sense-amplifier in response to a power control signal; and a second precharge unit suitable for individually changing each voltage level of the first and second bit lines based on a precharge control signal.

The invention provides a nanotube memory structure and a preparation method thereof. The nanotube memory structure comprises the components of a semiconductor substrate with a heavily doped epitaxiallayer on the surface; a first isolating dielectric layer, a ground selecting gate electrode layer, a bit line gate electrode layer, a string selecting gate electrode layer, and multiple second isolating dielectric layers among the ground selecting gate electrode layer, the bit line gate electrode layer and the string selecting gate electrode layer, wherein the first isolating dielectric layer, theground selecting gate electrode layer, the bit line gate electrode layer, the string selecting gate electrode layer and the multiple second isolating dielectric layers are arranged on the semiconductor substrate; a semiconductor channel which penetrates through the ground selecting gate electrode layer, the bit line gate electrode layer and the string selecting gate electrode layer; and a gate electrode dielectric layer which packages the sidewall of the semiconductor channel, wherein the semiconductor channel is a semiconductor nanotube on the heavily doped epitaxial layer. According to thememory structure, the semiconductor nanotube which epitaxially grows on the heavily doped epitaxial layer is used as the vertical channel; and compared with an existing vertical channel type NAND structure, the nanotube memory structure has advantages of further simplified device structure, easy controlling for the preparation process, and high yield rate of products.

According to an aspect of one embodiment, it is provided that semiconductor memory device determining a data read time required to read data from a memory cell by an operation to read a replica cell to which a replica bit line having a load equivalent to a bit line to be connected to the memory cell and a replica word line are connected, the semiconductor memory device comprising: a write control signal generating unit that includes logic gates coupled in multi stages for receiving an input of a replica word line activating signal generated in response to a driving signal for driving the replica word line, the write control signal generating unit generating a write control signal to determine a data write time required to write data in the memory cell based on the replica word line activating signal.

Provided is a semiconductor memory device including: first and second SRAM cells; a first bit line pair provided with the first SRAM cell; a second bit line pair provided with the second SRAM cell; a first switch circuit provided between the first bit line pair and the second bit line pair; and a controller that controls the first switch circuit to render the first bit line pair and the second bit line pair conductive, in a case of testing the first SRAM cell.