Semiconductor memory device for low power condition

[0086] Hereinafter, a semiconductor memory device for operating under a low power condition according to the present invention will be described in detail referring to the accompanying drawings.

[0087]FIG. 7 is a block diagram showing a core area of a semiconductor memory device in accordance with an embodiment of the present invention.

[0088] As shown, the semiconductor memory device includes a first reference cell block 400a, a second reference cell block 400b, a first cell array 300a, a second cell array 300b and a sense amplifying block 200.

[0089] Herein, each cell array, e.g., 300a, includes a plurality of unit cells, each for storing a data and outputting the data to one of a bit line and a bit line bar in response to inputted address and command; and the sense amplifying block 200 is for sensing and amplifying data outputted from each cell array. The first cell array 300a is coupled to the sense amplifying block 200 through a plurality of bit lines, e.g., BLn and BLn+1. The sec