69 results about "Storage cell" patented technology

Described herein are techniques for storing data in a redundant manner on a plurality of storage units of a storage system. While all of the storage units are operating without failure, only error-correction blocks are stored on a first one of the storage units, while a combination of data blocks and error-correction blocks are stored on a second one of the storage units. Upon failure of the second storage unit, one or more data blocks and one or more error-correction blocks formerly stored on the second storage unit are reconstructed, and the one or more reconstructed data blocks and the one or more reconstructed error-correction blocks are stored on the first storage unit.

A data element can be encoded into multiple encoded data elements using an encoding algorithm that includes an encoding function and one or more encoder constant. The encoded data elements can be organized into multiple pillars, each having a respective pillar number. Each of the pillars is sent to a different storage unit of a distributed storage network. To recover the original data element, the encoded data elements are retrieved from storage, and the encoder constant is recovered using multiple encoded data elements. Recovering the encoder constant allows the encoding algorithm originally used to encode the data elements to be determined, and used to recover the original data element. The security of the stored data is enhanced, because an encoded data element from a single pillar is insufficient to identify the encoder constant.

The invention provides systems and methods for control of power charge/discharge from energy storage system. The invention also provides for power monitoring and management. A smart charge system may include a system sensor, one or more energy storage units, and a controller, which may receive information about the power demand, power provided by an electricity provider, and charge/discharge information from an energy storage unit. The information received may all be time synchronized in relation to a time based reference. The controller may provide instructions to an energy storage unit at a rapid rate.

A phase change memory device includes a memory cell having a phase change material, a write driver which supplies a step-down set current to the memory cell, where the step-down set current includes a plurality of successive steps of decreasing current magnitude, and a set program control circuit which controls a duration of the step-down set current supplied by the write driver.

According to one embodiment, a nonvolatile memory device includes: a memory cell array including memory cells each having a variable resistance element for nonvolatilely storing data identified by an electrically rewritable resistance value; a first data latch storing write and erase data to be written on a given group of memory cells of the memory cell array for a write and erase operation; and a second data latch storing reference data for performing a compensation operation of the given group to compensate write and erase disturbance accompanied by the write or erase operation.

An image processing apparatus having a slideshow function includes: a storage unit that stores files corresponding to a plurality of images; a display unit that displays the plurality of images; a slideshow performing unit that reads the files from the storage unit and sequentially displays the plurality of images on the display unit in a slideshow function; a user input unit that receives input manipulation of a user and generating a signal; and an image processor that performs image processing on the files corresponding to images selected from the plurality of images displayed on the display unit based on the signal of the user input unit after the slideshow performing unit completes the slideshow function.

The invention provides a driving device for a light-emitting component. The driving device comprises a driving circuit, a storage unit, a resetting circuit, a first switch and a compensating circuit, wherein the driving circuit determines a current on a driving end according to a voltage on a control end thereof; the storage unit is arranged for keeping the voltage on the control end of the driving circuit; the resetting circuit is arranged for providing a resetting voltage to the control end of the driving circuit during the resetting process; a first end of the first switch is arranged for receiving a data voltage; a control end of the first switch is arranged for receiving a scanning voltage; and the compensating circuit is connected between a second end of the first circuit and the control end of the driving circuit so as to transmit the data voltage provided by the first switch to the control end of the driving circuit. The driving current generated by the driving device for a light-emitting component is not affected by a critical voltage of a transistor so each pixel of the light-emitting component on a display panel can acquire a same luminance according to the data voltage.

The invention belongs to the technical field of ferroelectric memories and particularly relates to a non-volatile ferroelectric memory with high read current and an operation method thereof. Each storage unit of the non-volatile ferroelectric memory is of an in-plane capacitor structure or up-down capacitor structure; polarization directions of ferroelectric materials are respectively vertical to electrodes; when enough large write voltage opposite to an electric domain polarization direction of a ferroelectric is applied to the two electrodes, ferroelectric domains in the corresponding regions of the electrodes are inversed from the polarization direction along an electric field direction, the electric domain polarization direction between the electrodes is opposite to the peripheral ferroelectric domain polarization direction, a domain wall is formed between the two electric domains, and the domain wall is usually an electric channel; when information is read, the read current of the electric channel is directly proportional to the perimeter of the electric domain wall, the longer the perimeter of the electric domain wall is, the larger the read current is. According to the ferroelectric memory of the invention, the read current in the storage unit can be improved to be helpful for improving the read speed of data and the reliability.

The present invention relates to a non-volatile ferroelectric memory device including a semiconductor active layer, a plurality of memory cells connected in series on the semiconductor active layer, and a control circuit for performing a read operation and a program operation on the selected memory cell among the plurality of memory cells, each of the memory cells comprising a para-dielectric layer on the semiconductor active layer; a dielectric stack including a ferroelectric layer stacked on the para-dielectric layer and a charge trap site for generating a negative capacitance effect of the ferroelectric layer by charges disposed and trapped at an interface between the ferroelectric layer and the para-dielectric layer; and a control gate electrode on the ferroelectric layer.

A non-volatile memory device and an operating method thereof are provided. The non-volatile memory device includes a memory unit including a plurality of memory blocks and a cam block, a peripheral circuit unit configured to program memory cells included in the plurality of memory blocks and the cam block or read programmed data, and a processor configured to control the peripheral circuit unit to measure an offset voltage by memory cell group in the plurality of memory blocks to set a read voltage during a test read operation and control the peripheral circuit unit to perform a read operation by memory cell group by using a new read voltage during a read operation.

A bicycle shift control device is adapted to be mounted to a bicycle equipped with an alternating current generator and a shifting device having a plurality of speed steps. The shift control device includes a power storage unit adapted to store electrical power from the alternating current generator; a shift control element operatively coupled for receiving electrical power from the power storage unit and for providing shift control signals for controlling the operation of the shifting device; and a case adapted to be mounted to the bicycle, wherein the case houses both the power storage unit and the shift control element.

A method of testing a semiconductor apparatus performs a function test of reading data from memory cells in SRAM by applying a potential lower than a GND potential to a backgate of an n-type MOS transistor with a drain connected with a storage node and a source connected with the GND potential. Then, the method performs a function test of reading data from memory cells by applying a potential higher than the GND potential to the backgate.

A semiconductor memory device for reading or writing data from or to a memory cell includes at least one cell array having a plurality of memory cells for outputting a stored data to one of a bit line and a bit line bar in response to inputted address and command; at least one reference cell array for outputting a reference signal to the other of the bit line and the bit line bar; a precharge block for precharging the bit line and the bit line bar as a ground; and a sense amplifying block for sensing and amplifying the data by using a core voltage for operating the semiconductor memory device and a high voltage having a higher voltage level than the core voltage.

An apparatus for determining whether or not a program violates a convention, including an input unit for receiving an input of a target program to be an object of a determination on whether to violate the convention; a violation storing unit for beforehand storing any one of an abstract syntax tree and a pattern which indicate a structure of a program violating the convention; a converter for converting the abstract syntax tree of the target program to a conversion tree with a predetermined conversion rule; and a determination unit for determining that the target program violates the convention on condition that at least a part of the conversion tree agrees with an abstract syntax tree violating the convention.

The present invention discloses a read and match circuit for a low-voltage content addressable memory, wherein the write circuit inputs the signals needing storing into the memory cells, and the read circuit retrieves the stored signals from the memory cells, and the match circuit compares the data stored in the memory cell with the data searched by the match circuit. As the circuits for writing, reading and matching are separated from each other and exempt from mutual interference, the present invention can achieve high reliability and low power consumption under a low-voltage operation environment without using a special fabrication process. In the present invention, the circuit is optimized to meet different requirements. The present invention enables the user to determine whether to have high speed or to have low power consumption. Further, the present invention can overcome the problems of current leakage and noise allowance in a low-voltage environment.

An image processing system which can execute various image processings in an operation process of a robot is provided. The image processing system includes: a robot for performing a predetermined operation on a workpiece; a photographing unit for photographing the workpiece; an acquisition unit for acquiring a position of the robot; a field programmable gate array (FPGA) for reconfiguring an internal circuit configuration; a storage unit for storing area information where circuit information for implementing predetermined image processing on an image obtained from the photographing unit as information for defining the circuit configuration of the FPGA is defined for each operation area of the robot; and a reconfiguration unit for reconfiguring the circuit configuration of the FPGA with the circuit information associated with the operation area based on that a position of the robot sequentially acquired by the acquisition unit belongs to one operation area defined in the area information.

The invention discloses a temperature and humidity monitoring and alarming system, which comprises a singlechip and an information acquisition module, and is characterized in that the singlechip comprises a data storage unit, a rule storage unit and a data analysis unit; the information acquisition module comprises a temperature sensor and a humidity sensor; the temperature sensor is connected with the data storage unit of the singlechip through an analog-to-digital converter; the humidity sensor is directly connected with the data storage unit of the singlechip; a keyboard system is connected with the rule storage unit of the singlechip through a man-machine conversation interface; and an alarming system and a display system are connected with the data analysis unit of the singlechip through the man-machine conversation interface. By adopting a detection system, the temperature and humidity monitoring and alarming system is simple in structure, small in size, high in instantaneity and favorable for acquiring ambient temperature and humidity in real time.

The present invention relates to a memory with a self-test function and a method for testing the same. The memory comprises a testing unit, a memory unit, and a comparison module. The method for testing the memory comprises steps of the testing unit producing a pattern signal; a first storage block of the memory unit storing storage data, and outputting the storage data according to the pattern signal; a second storage block of the memory storing a compare signature corresponding to the storage data; and the compare module producing a test signature according to the storage data output by the memory unit, and comparing the test signature to the compare signature and outputting a testing result for judging validity of the memory unit. Thereby, the memory unit according to the present invention is partitioned into two storage blocks for storing the storage data and the compare signature, respectively, and thus achieving the purposes of saving the testing time, costs, and hardware resources.

The present invention provides a projection type dish-ordering system. Said dish-ordering system includes dining table whose tabletop can be used as projection surface, control unit at least including operation processing unit and storage unit and projector. Said invention also provides its concrete operation method and steps.