39results about "Electronic circuit testing" patented technology

A plurality of test target chips on a test target wafer are simultaneously and electrically coupled to a plurality of chips on a test wafer via a wafer contactor. Each chip on the test wafer has a test circuit for conducting an operation test on each chip on the test target wafer. Since the test circuit is in a one-to-one relationship with respect to the test target chip, and is arranged on the test wafer other than the test target wafer, the many chips can be simultaneously tested in parallel during the wafer test without increasing an area of the test target chips.

The invention relates to an online intelligent fault diagnosis method of a power electronic circuit based on FRFT and IFSVC, which belongs to the field of signal processing and power electronic fault test. The method comprises the following steps: acquiring outputting signals of a to-be-tested power electronic circuit periodically at the proper testable node of a circuit; converting the acquired voltage or current signals in the way of FRFT to extract fault characteristics so as to form samples; and using a fault dictionary to work out so as to locate fault elements. The invention has the advantages of simple method, higher fault distinguishability, diagnosis accuracy, and the like; in addition, the invention can also improve the automation degree of the online fault diagnosis of the power electronic circuit.

A fabrication process produces markers for a magnetomechanical electronic article surveillance system. The marker includes a magnetomechanical element comprising one or more resonator strips of magnetostrictive amorphous metal alloy; a housing having a cavity sized and shaped to accommodate the resonator strips for free mechanical vibration therewithin; and a bias magnet to magnetically bias the magnetomechanical element. The process employs adaptive control of the cut length of the resonator strips, correction of the length being based on the deviation of the actual marker resonant frequency from a preselected, target marker frequency. Use of adaptive, feedback control advantageously results in a much tighter distribution of actual resonant frequencies. Also provided is a web-fed press for continuously producing such markers with adaptive control of the resonator strip length.

Initially, non-uniformity of statistical skews between a plurality of clock output terminal pairs is calculated. Next, a partial circuit driven by a clock output terminal pair having each skew distribution is extracted from an integrated circuit. Next, a second statistical timing characteristic which is a maximum value in the partial circuit is obtained from a first statistical timing characteristic of signal paths included in the extracted partial circuit. Next, timing verification for the integrated circuit is performed using the second statistical timing characteristics corresponding to the respective statistical clock skews.

This invention describes a method of synchronizing test clocks in an LSSD system to achieve near simultaneous arrival of the clock signals at the inputs of all LSSD registers. The method relies on pipelining the latches to distribute the test clocks, where all pipeline latches are synchronized by the system clock. This enhancement improves the frequency at which the test clocks switch and improve the testing throughput by reducing testing time, resulting in significant reductions in testing hardware and overall time required for system test, without compromising any of the benefits associated with conventional LSSD techniques. The method further enhances the distribution of the test clock signals to points throughout the entire chip, with a distribution network that is tailored according to a desired LBIST speed.

The invention discloses a method for rapidly creating an integrated circuit test program package, which comprises the following steps of: (1) a step of generating a configuration file; (2) a step of trimming test timing; (3) a step of converting a vector; and (4) a step of compiling a testing file. According to the invention, a signal name can be extracted from the VCD (Video Compact Disc) simulation vector; the error is avoided being introduced by manual input; by timing trimming before conversion, the workload of compiling and debugging is reduced; by adopting a batch conversion mode, the manual intervention is avoided and the interruption time of the conversion process is saved; timing information is extracted in a variable representation mode and the method can be directly used for down debugging or overclock testing of a DUT (Device Under Test).

The invention discloses a chip-based side channel leakage analysis system and method. The system comprises a chip carrier, a probe seat, a probe, an information acquisition module and a workstation. The chip carrier is used for carrying a chip to be tested, the probe seat is used for carrying the probe, and the probe is used for obtaining information leakage of a target trace inside the chip to betested. The information acquisition module is connected with the probe and used for acquiring information leakage obtained by the probe. The workstation is connected with the information acquisitionmodule and used for processing and analyzing the information leakage acquired by the information acquisition module. The side channel leakage analysis system and method introduce the probe, and directly obtain the information leakage of the target trace inside the chip through the probe. Thus, the accuracy of an attack and the signal-to-noise ratio of the obtained curve can be improved, and certain security measures can be selectively bypassed to achieve a more comprehensive security assessment with practical operability.

The invention provides an aging method based on the electric device with heat receiver, which makes the electric device on working condition at normal temperature environment and controls the heat receiver of the electric device to age the electric device.

The invention discloses a testing method for the step response performance of a phase-locked loop system, aiming at improving the testing precision of the step response performance. The testing method comprises the steps as follows: during the process that the phase-locked loop system steps from one stable oscillating frequency to another oscillating frequency, the waveform of an output voltage signal is recorded; the frequency information of the output voltage signal during the stepping process is obtained according to the waveform; and parameters of the step response performance are obtained according to the frequency information. The invention avoids leading testing parameters from a feedback loop, can not lead noise to an original system and improves the measuring precision.

A method for measuring an integrated circuit (IC) structure by measuring an imprint of the structure, a method for preparing a test site for the above measuring, and IC so formed. The method for preparing the test site includes incrementally removing the structure from the substrate so as to reveal an imprint of the removed bottom surface of the structure in a top surface of the substrate. The imprint can then be imaged using an atomic force microscope (AFM). The image can be used to measure the bottom surface of the structure.

In the manufacture of RFID tags, electronic components are connected with soldered connections to antennas stamped from a thin strip of electrically conductive metal, utilizing methods and intermediate products which enable accurate registration of the leads of the electronic components with contacts on the antennas. Thus, a strip of metal is provided with contact members unitary with the strip and coupled to the strip through compliant coupling arrangements which allow compliant movement of the contact members relative to the strip for accurate alignment with electronic components juxtaposed with the contact members for soldered connections between the leads of the electronic components and the corresponding contact members. The antennas, with the electronic components soldered in place, are carried by a substrate, and the sequence of the stamping and soldering operations avoids exposing the substrate to the heat of soldering.

The invention discloses a track circuit fault automatic diagnosis method based on a deep convolutional neural network, and the method comprises the steps: firstly obtaining the real-time change data of a track circuit, building a track circuit fault type data set, and dividing the data set into a training sample and a test sample; secondly, establishing a one-dimensional deep convolutional neuralnetwork, inputting the training set sample to train a network model, and evaluating the accuracy of the network model through a test sample to obtain a trained one-dimensional deep convolutional neural network model; and finally, inputting the real-time change data of the track circuit into the trained deep convolutional neural network model, establishing a mapping relationship between input and output through a neural network, outputting a fault type, and positioning a fault position. According to the method, the fault diagnosis efficiency and accuracy of the track circuit can be improved, field maintenance personnel can quickly process faults, and the maintenance and repair efficiency and the intelligent level of the track circuit are improved.

The invention discloses a method for testing chip parameters at different temperatures. The method comprises the following steps: chip automation testing equipment sends a temperature setting signal to a heat flow cover, wherein the temperature setting signal comprises a current preset temperature point; a temperature setting completion signal sent by the heat flow cover is received, wherein the temperature setting completion signal is a signal fed back to the chip automation testing equipment by the heat flow cover when the temperature of a chip reaches the preset temperature point after theheat flow cover provides an environment temperature for the chip according to the current preset temperature point and detects the temperature of the chip after receiving the temperature setting signal; performance testing is performed on the chip; and the steps are repeated after the testing is completed, and the performance testing is performed on the chip according to a plurality of preset temperature points. According to the method for testing the chip parameters at the different temperatures, the workload of workers can be reduced, all tests can be completed by periodically replacing thechip, and the test efficiency of the chip is improved.

The invention discloses a functional tester with an elastic connector. The functional tester comprises a base, a bracket, a TP (touch panel) screen body for testing, a dual-head probe and the elastic connector, wherein the base comprises a top plate and a bottom plate; based on a using direction, one end of the bracket is fixed at the upper surface of the top plate, and the lateral part of the other end of the bracket is fixedly connected with a first locating mechanism; the first locating mechanism can be located on the upper surface of the top plate and separated from an FPC (flexible printed circuit) to be tested; a second locating mechanism is additionally arranged on the top plate and can be located on the lower surface of the top plate and separated from the TP screen body for testing; the TP screen body for testing is electrically connected with the FPC to be tested through the probe; the connector is located and fixed on the top plate; and one end of the connector is elastically and electrically connected with the FPC to be tested, and a lead for educing signals is arranged at the other end of the connector. The functional tester has the advantages that the structure is simple, the implementation and operation are simple, the damage to the test connector can be effectively reduced, the use times of the test connector increase, manpower can be saved, the work efficiency can be improved and the like.

The invention discloses a method of solving non-monotonous POWERGOOD signals in a VR power-failure sequential test. The method comprises the step of loading small amount of current at a POWERGOOD signal line pulling-up power supply of a VR chip. The invention also discloses a system of solving non-monotonous POWERGOOD signals in a VR power-failure sequential test. According to the invention, the problem of non-monotonous POWERGOOD signals in a VR power-failure sequential test can be precisely and quickly solved; real working conditions of the VR are reflected; test efficiency is improved; andthe method and the system are simple and highly efficient.

A first A/D converter converts an analog observed value, which corresponds to a power supply signal supplied to a power supply terminal of a DUT, into a digital observed value. By means of digital calculation processing, a digital signal processing circuit generates a control value that is adjusted such that the digital observed value matches a predetermined reference value. A first D/A converter supplies, via a power supply line to the power supply terminal of the DUT, an analog power supply signal obtained by performing digital/analog conversion of the control value. A load estimating unit applies a test signal containing a predetermined frequency component via the power supply line to a node via which the power supply terminal is to be connected, and generates a control parameter for the digital signal processing circuit according to the test signal and the observed signal.

An aging room used for the last assembling process of LCD panel modules includes a primary test area, a heating area, a constant temperature area, a cooling area, a full test area and a trolley cycle area. It also includes a loading track, a heating track, an aging test track, a cooling track, a full test track and a trolley cycle track that lies in each said area correspondingly. In correspondence with the sizes of LCD panels, various inlets are disposed in the outward wall of the primary test area; various trolleys used for carring LCD panels are provided on the tracks; various aging test tracks that have different lengths according to the aging times necessary for each size of LCD panels are provided in the constant temperature area; and various outlets are provided. Accordingly, the aging room could test various sizes of LCD panels in the same time, thus reduces the wait time for aging test and increase the efficiency. Furthermore, the trolleys are used circularly in the aging room such that the energy loss is reduced.

The present invention relates to a memory with a self-test function and a method for testing the same. The memory comprises a testing unit, a memory unit, and a comparison module. The method for testing the memory comprises steps of the testing unit producing a pattern signal; a first storage block of the memory unit storing storage data, and outputting the storage data according to the pattern signal; a second storage block of the memory storing a compare signature corresponding to the storage data; and the compare module producing a test signature according to the storage data output by the memory unit, and comparing the test signature to the compare signature and outputting a testing result for judging validity of the memory unit. Thereby, the memory unit according to the present invention is partitioned into two storage blocks for storing the storage data and the compare signature, respectively, and thus achieving the purposes of saving the testing time, costs, and hardware resources.

A computer-implemented method of measuring bridge fault coverage for a test pattern for a circuit design to be implemented within a programmable logic device can include identifying simulation results and stuck at coverage of the circuit design for the test pattern (610, 620). Pairs of nets in the circuit design that are adjacent can be identified (625). Each type of bridge fault for which each pair is tested can be determined according to the simulation results (640, 645, 655, 660). A measure of bridge fault coverage for the test pattern can be calculated according to which types of bridge faults each pair is tested and which net of each pair acts as an aggressor for each type of bridge fault tested (675). The measure of bridge fault coverage can be output (680).

The invention provides a driving chip fault detection method, a driving chip and a main control chip. A communication line special for information transmission is arranged between the driving chip andthe main control chip. The method comprises the steps that the driving chip receives a driving signal sent by the main control chip, and an insulated gate bipolar transistor (IGBT) is driven by the driving signal to work; the driving chip performs fault detection on working parameters of the IGBT and the driving signal; and when it is detected that the IGBT and/or the driving signal have/has a fault, the driving chip feeds fault information back to the main control chip through the communication line, wherein the fault information comprises a fault type. Therefore, the driving chip can feed the fault information back to the main control chip through the communication line.

A touch panel producing method includes the following steps. Firstly, a first coiled sheet and a second coiled sheet are transferred in a specified direction. Then, the first coiled sheet and the second coiled sheet are laminated together. Then, a laminated structure of the first coiled sheet and the second coiled sheet is cut, so that a sensing plate section is produced. Then, the sensing plate section is removed from the laminated structure of the first coiled sheet and the second coiled sheet, so that a sensing plate is produced. Afterwards, a touch control circuit board is attached on the sensing plate. The first coiled sheet includes plural sensing regions. The second coiled sheet is an adhesive sheet. The sensing plate section includes one of the plural sensing regions.

The invention relates to an elastic deformation adjusting device for a middle frame plate of an FCT tester. The elastic deformation adjusting device comprises a pressing plate module, a needle carrierplate module, a strain gauge, a middle frame plate module, a dynamic control module and a driving module. The middle frame plate module is installed on an in-out driving module, strain gauges are installed on the middle frame plate module at equal intervals, and the strain gauges are connected with the stress analysis module to provide real-time deformation data for the stress analysis module. The dynamic control module uses the stress analysis module to collect middle frame plate module deformation real-time data input by the strain gauges, and controls the deformation of the middle frame plate module by adjusting upper and lower driving modules. According to the invention, the deformation quantity of the middle frame plate can be monitored in real time, the air pressure of a pressure regulating valve is dynamically regulated, and poor contact of a probe caused by excessive deformation of the middle frame plate is prevented.

A spare column on which spare memory cells are arranged is provided in a memory cell array. In the memory cell array, address assignment can be altered so that sub-word lines selected collectively according to the same row address is divided into the right and left halves. The alteration in assignment can be realized by disconnecting a fuse element incorporated in a SD generating circuit. Even in a case where a plurality of defective memory cells are concentrated on the same memory cell row, the number of defective memory cells in a select unit corresponding to row address can be altered by alteration in address assignment so as to be reduced as a result of distribution; thereby enabling increase in number of chips that can be saved with spare memory cells. Accordingly, improvement on saving rate for defective chips can be realized without increasing the number of spare memory cells.

A test pin for a test device for electrically contacting a device under test to be tested, wherein the test pin comprises an electrically conductive base structure for electrically conducting a test signal between the device under test and the test device, and an exchangeable electrically conductive pin tip body configured to directly contact the device under test and to be exchangeably assembled with the base structure.

A handler apparatus adjusts a position of an actuator and enhances positional accuracy of a device under test. Provided is a handler apparatus that conveys a device under test to a test socket, including: an actuator that, prior to fitting of a device holder holding the device under test to the test socket, fits the device holder, and adjusts a position of the device under test on the device holder; and an actuator adjusting section that adjusts an amount of driving of the actuator by causing the actuator to fit an actuator fitting unit.