Semiconductor test device for conducting an operation test in parallel on many chips in a wafer test and semiconductor test method

Referring to FIG. 1, a test target wafer 10 to be tested has a plurality of chips CP. FIG. 1 shows chips CP-n and CP-(n+1) in the nth (n: natural number) and (n+1)th positions among these plurality of chips CP. An electrode pad 12 allowing input / output of an electrical signal is arranged on each chip, and a bump 14 is also provided for achieving a good electrical contact between electrode pad 12 and an external system.

Semiconductor test device 100 according to the first embodiment includes a wafer contactor 20 and a test board 150. Wafer contactor 20 includes a plurality of contact terminals 22 provided corresponding to the plurality of bumps 14, respectively. Each contact terminal 22 can be in electrical contact with bump 14, and thereby can be electrically coupled to corresponding electrode pad 12 on chip CP simultaneously. Test target wafer 10 including bumps 14 and wafer contactor 20 are similar to those shown in FIGS. 23 and 24, and therefore description thereof is not repeated.

As a second embodiment of the invention, description will now be given on a structure for performing a wafer test, in which a test wafer which carries a circuit having a test function is used corresponding to test target wafer 10, and is connected thereto via a wafer contactor for performing the wafer test.

Referring to FIG. 4, semiconductor test device 200 according to the second embodiment differs from semiconductor test device 100 shown in FIG. 1 in that a test wafer 210 and a wafer contactor 220 are further employed. Test wafer 210 has a plurality of chips SCP corresponding to the plurality of chips CP on test target wafer 10, respectively. In semiconductor test device 200, the circuit for performing the self-test corresponding to the BIST function is not arranged on the test board 150, but is arranged on test wafer 210. On test wafer 210, electrode pads 212 and 214 are arranged similarly to test target wafer 10.

Wafer contactor 220 is provided for ensuring electrical contact between

As a third embodiment, description will be given on a structure, in which a portion of components of the self-test circuit is mounted on the chip to be tested.

Referring to FIG. 9, self-test circuit STR further includes a redundant repair determining portion 166, which performs determination relating to redundant repair based on the test data, in addition to test pattern generating portion 160 for generating a test pattern signal and PASS / FAIL determining portion 164 receiving test data issued from the test target in response to the test pattern signal. Redundant repair determining portion 166 determines presence / absence of a defective portion, and analyses an address of the defective portion based on the test data. Redundant repair determining portion 166 issues redundant repair data including a defective address indicative of the defective portion. Although not shown, the structure may be additionally provided with a portion for storing redundant repair data.

The test target in whi