42results about "Pulse automatic control" patented technology

A novel and useful apparatus for and method of software based phase locked loop (PLL). The software based PLL incorporates a reconfigurable calculation unit (RCU) that is optimized and programmed to sequentially perform all the atomic operations of a PLL or any other desired task in a time sharing manner. An application specific instruction-set processor (ASIP) incorporating the RCU includes an instruction set whose instructions are optimized to perform the atomic operations of a PLL. A multi-stage data stream based processor incorporates a parallel/pipelined architecture optimized to perform data stream processing efficiently. The multi-stage parallel/pipelined processor provides significantly higher processing speeds by combining multiple RCUs wherein input data samples are input in parallel to all RCUs while computation results from one RCU are used by adjacent downstream RCUs. A register file provides storage for historical values while local storage in each RCU provides storage for temporary results.

A system for stabilizing a delay through a signal path of an integrated circuit (IC) includes an oscillator for producing a periodic first reference signal, a delay circuit for delaying the first reference signal to produce a periodic second reference signal, and a loop controller for adjusting the magnitude of the IC's power supply so as to maintain a constant phase difference between the first and second reference signals. By adjusting the power supply magnitude, the loop controller also stabilizes signal path delays through logic circuits implemented in the IC. The oscillator is formed by a logic gate implemented in the IC and a passive delay line feeding the logic gate's output back to its input. The delay of the delay circuit is programmably adjustable to allow for adjustment of the signal path delay through the IC.

A semiconductor integrated circuit having a built-in PLL circuit which has two charge pump circuits for charging and discharging capacitive elements of a loop filter in response to signals generated by a phase comparator circuit. One of the two charge pump circuits has current sources which generate current values smaller than those generated by current sources of the other charge pump circuit. The loop filter has a first capacitive element connected to a charge/discharge node, and a second capacitive element connected to the charge/discharge node through a resistive element. The first capacitive element is charged and discharged by the one charge pump circuit, while the second capacitive element is charged and discharged by the other charge pump circuit. A charging current source of the one charge pump circuit operates simultaneously with a discharging current source of the other charge pump circuit, i.e., the charge pump circuits operate in opposite phase.

Measurement circuit components are included in an integrated circuit fabricated on a semiconductor substrate. These measurement circuits are connected to a voltage regulation circuit that provides the integrated circuit voltage source. These measurement circuits provide signals to control the voltage regulation circuit to adjust the voltage output to the integrated circuit based upon a measurement values obtained on the semiconductor device. These measurements include temperature and IR drop at locations on the semiconductor substrate, along with the frequency response of integrated circuit.

The present invention discloses a host receiver synchronizer for passive optical networks, and in particular a burst clock data recovery circuit in a host receiver in a bursty asynchronous communication system having a non-data preamble of less than 250 ns, for recovering a clock signal from a subscriber data burst. The circuit comprises: an adjustable oscillator for generating an output clock signal in response to a signal at an input thereof; a first comparator for comparing a frequency and phase of the output clock signal to that of a reference signal and feeding back a first feedback signal to the oscillator input; and a second comparator for comparing the frequency and phase of the output clock signal to that of the data burst and feeding back a second feedback signal to the oscillator input once the output clock signal is locked in frequency with the reference signal. The output clock signal is locked in frequency and phase to the data burst before receipt of the last bit of the preamble. The present invention is advantageous in that the receiver circuit improves synchronized jitter performance over the prior art solutions so that additional timing margin is provided, thereby allowing longer fiber lengths to be supported.

There is provided an oscillator including: a reference signal generator that generates a reference signal having a reference frequency; a phase comparator that outputs a voltage in accordance with a phase difference between the reference signal and a feedback signal; a loop filter that receives a voltage output from the phase comparator, and gain-adjusts a voltage output from the phase comparator by means of an external control signal; a voltage controlled oscillator that oscillates an output signal at a frequency in accordance with an adjusted signal having been gain-adjusted by the loop filter; and a frequency divider that feeds back a frequency-divided signal resulting from frequency-dividing the output signal, to the phase comparator as the feedback signal.

An output drive circuit of an output buffer circuit has a signal output line and first, second and third switching circuits connected to the signal output line at different locations thereof. Each of the first, second and third switching circuits includes one of first switching devices connected between a power source line and the signal output line, and one of second switching devices connected between the signal output line and a ground line. Each of the first, second and third switching circuits includes one of first control signal lines that turn on and off the first switching devices, respectively, and one of second control signal lines that turn on and off the second switching devices, respectively. Drivabilities of the first and/or the second switching devices in the switching circuits are set to gradually increase in a specified order.

A frequency synthesizing system includes a clock generator to generate a reference clock signal, a frequency doubler to generate a frequency-doubled clock signal in response to rising edges and falling edges of the reference clock signal, a frequency multiplier to generate a frequency-multiplied clock signal in response to either rising edges or falling edges of the frequency-doubled clock signal, and a fractional-N synthesizer coupled to the frequency multiplier to generate an output clock signal in response to the frequency-multiplied clock signal.

A circuit and method for calibrating a VCO (voltage controlled oscillator) is disclosed. In one embodiment, a circuit includes a VCO and a bias control circuit coupled to a tail node of the VCO. An amplitude control unit may also be coupled to the tail node, wherein the amplitude control unit is configured to determine the amplitude of a VCO output signal based on a voltage present on the tail node. The amplitude control unit may also be configured to generate a bias voltage based on the amplitude of the VCO output signal and a target voltage. The bias control circuit may be coupled to receive the bias voltage from the amplitude control unit and may be further configured to adjust the voltage on the tail node based on the received bias voltage.

A square-law clamping circuit (99, 120) sinks a current from an input/output terminal proportional to a square of a difference between a voltage thereon and a reference voltage. A first MOS transistor (130) has a source for receiving the reference voltage, a gate, and a drain coupled to its gate. A current source (134) coupled to the drain of the first MOS transistor (130) sources a predetermined current therefrom. A second MOS transistor (132) has a source providing the input/output terminal (100, 121), a gate coupled to the drain of the first MOS transistor (130), and a drain. A current sink (135) coupled to the drain of the second MOS transistor (132) sinks a current therefrom.

The invention discloses a testing method for the step response performance of a phase-locked loop system, aiming at improving the testing precision of the step response performance. The testing method comprises the steps as follows: during the process that the phase-locked loop system steps from one stable oscillating frequency to another oscillating frequency, the waveform of an output voltage signal is recorded; the frequency information of the output voltage signal during the stepping process is obtained according to the waveform; and parameters of the step response performance are obtained according to the frequency information. The invention avoids leading testing parameters from a feedback loop, can not lead noise to an original system and improves the measuring precision.

The invention discloses a broadband microwave frequency source circuit with low phase noise. The reference frequency is input into a digital phase detector and a low phase noise amplifier respectively. The output end of the digital phase detector is connected with the input end of a passive loop filter, and the output end of the passive loop filter is connected with the first end of a plurality ofactive loop filters respectively. The output of the low phase noise amplifier is connected to the input of the sampling phase detector. The output of the sampling phase detector is connected to the input of the first set of multiplexers, the output terminals of the first group of multiplexers are respectively connected with the second terminals of a plurality of active loop filters, the third terminals of the plurality of active loop filters are respectively connected with the input terminals of the second group of multiplexers, the output terminals of the second group of multiplexers are respectively connected with a plurality of VCOs, and a plurality of VCOs select one output. The selected VCO output signal is fed back to the sampling phase detector as the system output and fed back tothe digital phase detector through the N divider. The invention realizes the effects of wide frequency band and low phase noise.

An auto-nulled bandgap reference system employing a substrate bandgap reference circuit with primary and auxiliary amplifiers and a switching circuit which in a first mode develops a voltage to null the offset and noise errors of the auxiliary amplifier and then in the second mode uses the nulled auxiliary amplifier to develop a voltage to null the offset and noise errors of the primary amplifier; and a strobe circuit including an output storage device and a strobe control circuit for periodically powering up a bandgap reference circuit to charge the output storage device and powering down the bandgap reference circuit to conserve power.

The invention provides a method for outputting high-precision and high-frequency clock signals and an oscillating circuit. The oscillating circuit comprises a low-frequency oscillator, a high-frequency oscillator, a frequency regulator, a first input, a first output and a second output. Fine adjustment configuration signals are input into the low-frequency oscillator through the first input; the low-frequency oscillator outputs low frequency clock signals through the first output; meanwhile, the low frequency clock signals are input into the frequency regulator; the frequency regulator outputs automatic calibrating signals to the high-frequency oscillator through adjustment and compensation of the frequency regulator; finally, the high-frequency oscillator outputs the stable second output, namely high-frequency clock signals. Through the method for outputting the high-precision and high-frequency clock signals and the oscillating circuit, the high-precision and high-frequency clock signals can be output.

A phase locked oscillator includes a voltage control oscillator and a phase comparator for detecting a phase difference between a phase of an output signal of the voltage control oscillator and a phase of a reference signal and controlling a voltage to be applied to the voltage control oscillator based on the detected phase difference. The phase locked oscillator also includes a delay control part configured to apply a variable delay time to the output signal of the voltage control oscillator and a delay time controlling part configured to control the delay time according to the detected phase difference.

An electronic integrated circuit includes a first signal (A1) generated by a first source block (10) and a second signal (B1) generated by a second source block (12). A variable delay circuit (18) detects a delay between said first and second signals in calibration mode and applies the delay to the first signal during normal operation of the circuit. A fixed delay buffer (32) may be used to apply a delay to the second signal to compensate for known delays associated with the variable delay circuit (18).

The invention provides a phase locked loop and a voltage controlled oscillator. The voltage controlled oscillator comprises a ring oscillator unit and a control unit, wherein the ring oscillator unit is used for providing an output clock pulse signal, the control unit is coupled with the ring oscillator unit and used for receiving an output voltage so as to respectively provide a first voltage frequency grain and a second voltage frequency grain to control the frequency of the output clock pulse signal of the ring oscillator, and the first voltage frequency grain is greater than the second voltage frequency grain.

A charge pump control circuit that four main parts: a clock control circuit; a clock switch and driver circuit; a pump stage; and a dynamic load control circuit. The clock control circuit has a dynamic load that is controlled by the dynamic load control circuit. When the charge pump control circuit is enabled, the dynamic capacitive load is applied which incorporates a delay allowing the high frequency clock to control the pump stage and quickly charge the output to the desired boosted voltage. This provides a very fast boosted output voltage during a startup condition. Once the desired output voltage is realized, the dynamic capacitive load is disabled and the low frequency clock takes over the operation. During each low frequency clock cycle, the high frequency clock is enabled for several cycles per cycle of the low frequency clock.

A sync generator (genlock) (10) for frequency and phase locking an incoming video signal to a system clock (12) includes a digitizer (16, 22) for digitizing the incoming video signal to yield a digitized color sub-carrier burst component. A numerically controlled oscillator (15) clocked by the system clock generates a phase lock reference signal for locking to the incoming video signal. Phase detection means logic unit (42, 74) sense a static phase offset magnitude from an ideal 90° phase offset between the digitized color sub-carrier burst component and the numerically controlled oscillator output signal. In accordance with the sensed static offset, a static phase error nulling circuit (70) generates a compensating offset in accordance for input to the system clock (27) to drive the static offset to zero, thus achieving frequency and phase locking. A color frame logic unit (78) determines the color frame sequence for the purpose of resetting the NCO and generating a color frame pulse marking the start of the period sequence.

A U-band microwave direct modulation system comprises a C-band local oscillation circuit, a C-band amplification circuit, a U-band 8-frequency multiplication circuit, a U-band QPSK microwave direct modulation circuit and a level conversion circuit. The C-band local oscillator circuit takes a high-stability reference source as an input, performs sampling phase locking on the high-stability reference source, and generates C-band carrier waves with extremely low phase noise; the C-band amplifying circuit is used for carrying out power amplification and isolation on the C-band carrier with extremely low phase noise; the U-frequency band 8-frequency multiplication circuit is used for carrying out multiple harmonic frequency multiplication and isolation on the amplified and isolated C-frequencyband carrier wave with extremely low phase noise so as to generate a U-frequency band carrier wave; the level conversion circuit performs bipolar conversion on the external data to obtain bipolar level data; and the QPSK microwave direct modulation circuit of the U frequency band modulates the phase of the carrier of the U frequency band under the data driving of the bipolar level to realize QPSKmodulation so as to obtain a QPSK modulation signal, and the QPSK modulation signal is isolated and then output.

A mixer with a differential DC offset cancellation function includes: a load unit including a first load unit and a second load unit; a mixing unit biased by current transferred from the load unit to mix inputs signal and oscillation signals; a first output voltage detection unit detecting an output voltage of the first output terminal; a second output voltage detection unit detecting an output voltage of the second output terminal; a first injection/extraction circuit unit injecting current into the first load unit or extracting current from the first load unit according to the size of a first detection voltage; a second injection/extraction circuit unit injecting current into the second load unit or extracting current from the second load unit according to the size of a second detection voltage; and a current regulation unit regulating an overall current flowing across the first and second injection/extraction circuit units.

The present invention provides a method and system for open loop compensation of delay variations in a delay line. The method includes sensing the Process, Voltage, Temperature (PVT) variations in the delay line using a sensing circuit. A first and second sensitive current are generated based on the PVT variations. The first and second sensitive currents are mirrored currents from the sensing circuit. Then, a first compensation current is generated based on the first sensitive current and a first summing current. The first summing current is a reference current independent of the PVT variations. Further, the first compensation current is mirrored as a second summing current and a second compensation current is generated from the second sensitive current and the second summing current. The second compensation current compensates the delay variations and has a sensitivity based on the sensitivities of the first and second sensitive currents.