118results about "Digital storage" patented technology

In a shift register and an LCD having the same, the shift register includes stages having odd stages for receiving a first clock signal and even stages for receiving a second clock signal and all stages receive a control signal. Each of the stages includes a pull-up section for providing one of first and second clock signals to an output terminal, a pull-down section for providing a first power voltage to the output terminal, a pull-up driving section for turning on/off the pull-up section in response to the control signal, a first pull-down driving section for outputting a second control signal, and a second pull-down driving section for turning off the pull-down section in response to the input signal and turning on the pull-down section in response to the second control signal.

The method of operating the nonvolatile memory device may include performing a read operation on a first address region, comparing a read time of the first address region with a reference time, and storing read data from the read from the first address region in a second address region based on the comparison result.

A memory cell includes a magnetic cell junction having an antiferromagnetic layer within a portion of the cell junction that is adapted to characterize a logic state of a bit written to the junction. More specifically, a memory cell includes, an antiferromagnetic layer arranged in contact with an adjacent magnetic layer within a storing portion of a magnetic cell junction. Such a magnetic cell junction configuration and a method for programming a memory cell with such a cell junction configuration may be used to improve the write selectivity of a memory cell array and reduce the amount of current needed to write a bit to a memory cell. Moreover, a memory cell includes a magnetic cell junction having an aspect ratio less than 1.6. In addition, a memory cell includes at least two resistors.

The present invention defines a strong authentication token for generating different dynamic credentials for different application providers comprising an input interface providing an output representing an application provider indicator; a secret key storage for storing one or more secret keys; a variability source for providing a dynamic variable value; a key providing agent for providing an application provider specific key as a function of said application provider indicator using one or more keys stored in said secret key storage; a cryptographic agent for cryptographically combining said application provider specific key with said dynamic variable value using symmetric cryptography; a transformation agent coupled to said cryptographic agent for transforming an output of said cryptographic agent to produce a dynamic credential; and an output interface to output said dynamic credential.

The present invention defines furthermore a method to manage the secret keys of strong authentication tokens that can generate dynamic credentials for more than one supported application provider or application provider group using different secret keys for each supported application provider or application provider group comprising generating for each of a batch of strong authentication tokens a token specific master key; personalising each token of said batch with the token specific master key associated with said token; generating for each of a plurality of supported application providers or application provider groups a set of application provider specific token keys, one application provider specific token key for each token of said batch, whereby each application provider specific token key of each of said sets is derived from that token's token specific master key and a unique identifier or indicator of that application provider or application provider group; providing to each application provider or an entity that is responsible for the verification on behalf of said application provider of the dynamic credentials that are generated for said application provider, the corresponding set of application provider specific token keys.

An apparatus and method are disclosed for variable authentication requirements. The apparatus includes an operating status module identifying a change in an operating status of a device and maintaining a history of operating statuses, and an access control module comparing a current operating status with a previous operating status. The apparatus also includes a profile module maintaining a trust indicator for each operating status. The access control module determines a level of authentication required to unlock the device in response to the trust indicator associated with the current operating status. The method includes identifying a change in an operating status of a device and maintaining a history of operating statuses, and comparing a current operating status with a previous operating status. The method also includes maintaining a trust indicator for each operating status, and determining a level of authentication required to unlock the device in response to the trust indicator associated with the current operating status.

A method of managing an access right to at least one asset associated with at least one digital work order, to at least one first element associated with the at least one asset, or to at least one second element associated with an access path to the at least one asset or the first element, and relates to a system and a computer program for the same.

A gate driver includes several first and second circuit units outputting first and second driving signals to odd and even gate lines, respectively, and each of the first circuit units or the second circuit units includes a signal output unit for outputting the driving signal and a shift register unit for outputting a start signal to a next circuit unit. A driving method is also disclosed.

A system and method for using hierarchical policy levels for distribution of software in a computer network. In one embodiment, computers of the network are arranged into a hierarchy. A management policy server with access to the network queries the hierarchy to identify computers at or below its own level within the hierarchy. Once a set of computers is identified, software programs, updates or policies are distributed, bypassing human intervention.

A shift register having individual driving nodes is disclosed. The shift register includes a first clock pull-down module, a second clock pull-down module, a key pull-down module, a self feedback module, and a driving output unit. The first clock pull-down module is used to pull-down the potential of a gate line to a low voltage when the first clock signal is in a high voltage level. The second clock signal pull-down module pulls down the potential of the gate line to the low voltage when the second clock signal is in a high voltage level. The key pull-down module rapidly pulls down the potential of the gate line to the low voltage level after the gate line outputs an output signal. The self feedback module is used to output a driving signal to the key pull-down module. The driving signal output unit outputs a next stage driving signal which is irrelative to the operation of the previous stage shift register.

A cross point memory array includes a structure in which holes are formed in an insulating layer and a storage node is formed in each of the holes. The storage node may include a memory resistor and a switching structure. The master for an imprint process used to form the cross-point memory array includes various pattern shapes, and the method of manufacturing the master uses various etching methods.

An improved DDR interface uses single-ended technology and phase-shifts all output data signals and the output source clock signal so that each output signal switches at a different time so that IDDQ spikes caused by I/O switching do not accumulate. A dynamic phase adjustment circuit on the receiver compensates for the phase differences. Clock jitter and skew is reduced and the number of IDDQ pins is reduced to provide a more effective design and high density package.

A phase change memory device includes a memory cell having a phase change material, a write driver which supplies a step-down set current to the memory cell, where the step-down set current includes a plurality of successive steps of decreasing current magnitude, and a set program control circuit which controls a duration of the step-down set current supplied by the write driver.

A process and a memory architecture is based on “vertical” pages, and support byte by byte erasure. A byte within a “vertical” page is erased, and then other bytes within the “vertical” page sharing bit lines with the erased byte, are subjected to a program verify operation after exposure to the stress caused by the erase process. The other bytes in the page are re-programmed to recover the data if they fail verify. Therefore, byte erase is executed without the erase/re-program cycling, and only memory cells within the same vertical page as the erased byte, which suffer stress from the erase potentials on the shared bit lines sufficient to shift their thresholds out of range, are re-programmed.

A DRAM and memory controller are coupled during driver training to reduce mismatches. The impedances of the system are controlled through a termination at the controller to yield improvements in timing margins. The coupling of the components on a shared electrical bus through adjustment of the termination values during training removes known offset issues.

According to one embodiment, a nonvolatile memory device includes: a memory cell array including memory cells each having a variable resistance element for nonvolatilely storing data identified by an electrically rewritable resistance value; a first data latch storing write and erase data to be written on a given group of memory cells of the memory cell array for a write and erase operation; and a second data latch storing reference data for performing a compensation operation of the given group to compensate write and erase disturbance accompanied by the write or erase operation.

A method for reading a NAND flash memory device is provided. The NAND flash memory device includes a first bit line that is selected and a second bit line that is not selected. Each bit line is connected to a cell string including a string selection transistor, a plurality of memory cell transistors, and a source selection transistor connected in series. In the method, first, the first bit line is precharged while power supply voltage is applied to the second bit line. The string selection transistors are turned on and a read voltage is applied to a selected memory cell while a pass voltage is applied to unselected memory cells. The state of the selected memory cell transistor is detected according to whether or not charge precharged on the first bit line has been discharged.

Apparatus, systems, and methods are disclosed, such as those that operate within a memory device to replace one or more selected failing memory cells with one or more repair memory cells and to correct data digits read from other failing memory cells in the memory device using a different method. Additional apparatus, systems, and methods are disclosed.

Techniques for data storage are provided. In one aspect, a method for writing one or more magnetic memory cells comprises the following steps. Data is written to one or more of the magnetic memory cells. It is detected whether there are any errors in the data written to the one or more magnetic memory cells. The data is rewritten to each of the one or more previously written magnetic memory cells in which an error is detected.

A device includes first through third logic circuits. Each of first and second logic circuits includes a first circuit portion generating a first output signal in response to a first input signal when a second input signal takes a first logic level, and a second circuit portion transferring the first input signal to output the first output signal when the second input signal takes a second logic level. The third logic circuit includes a third circuit portion generating a second output signal in response to the first output signal supplied from the first logic circuit when the first output signal supplied from the second logic circuit takes a third logic level, and a fourth circuit portion generating the second output signal in response to the first output signal supplied with the first logic circuit when the first output signal supplied from the second logic circuit takes a fourth logic level.

An INVSRC node and a SAREF node are previously precharged. After a potential on a bit line is reset, the bit line (BLS node) is precharged. In this event, a clamp MOS transistor in a sense amplifier is in ON state, and an SA node is also precharged simultaneously. A precharge level is set to a value lower than a threshold voltage of an inverter. Subsequently, when SAEN transitions to “H,” a sense operation is performed. For reading data “0,” the SA node is rapidly increased to Vdd. For reading data “1,” the SA node slowly approaches to Vss. A change in the potential at the SA node is detected by the inverter.

A data output apparatus converts input data into data that changes less than the input data, and outputs the converted data to a memory.