135 results about "Hemt circuits" patented technology

The invention relates to a modular multilevel converter (MMC)-based transformer-free four-quadrant high-voltage variable frequency power supply topological structure. A rectifier module and an inverter module have a modular multilevel structure and are formed by a plurality of subunits connected in series. The input side of the topological rectifier module is directly connected with a network-side high voltage through a charging circuit; the rectifier module converts a high-voltage alternating current (AC) voltage into a direct current (DC) voltage and inputs the DC voltage into the inverter module, and the inverter module converts the DC voltage into the AC voltage; and various states of a power system are simulated, and the topological structure has a four-quadrant type and can feed energy back. The topological structure has the advantages of removing the high-voltage transformer at the power input end, lowering cost, reducing volume and weight of a high-voltage variable frequency power supply, reducing consumption of components, and improving work efficiency, has a simple unit structure, and is convenient to wire and easy to disassemble and assemble.

An INVSRC node and a SAREF node are previously precharged. After a potential on a bit line is reset, the bit line (BLS node) is precharged. In this event, a clamp MOS transistor in a sense amplifier is in ON state, and an SA node is also precharged simultaneously. A precharge level is set to a value lower than a threshold voltage of an inverter. Subsequently, when SAEN transitions to “H,” a sense operation is performed. For reading data “0,” the SA node is rapidly increased to Vdd. For reading data “1,” the SA node slowly approaches to Vss. A change in the potential at the SA node is detected by the inverter.

A system has a reduced sensitivity to Single Event Upset and/or Single Event Transient(s) compared to traditional logic devices. In a particular embodiment, the system includes an input, a logic block, a bias stage, a state machine, and an output. The logic block is coupled to the input. The logic block is for implementing a logic function, receiving a data set via the input, and generating a result f by applying the data set to the logic function. The bias stage is coupled to the logic block. The bias stage is for receiving the result from the logic block and presenting it to the state machine. The state machine is coupled to the bias stage. The state machine is for receiving, via the bias stage, the result generated by the logic block. The state machine is configured to retain a state value for the system. The state value is typically based on the result generated by the logic block. The output is coupled to the state machine. The output is for providing the value stored by the state machine. Some embodiments of the invention produce dual rail outputs Q and Q′. The logic block typically contains combinational logic and is similar, in size and transistor configuration, to a conventional CMOS combinational logic design. However, only a very small portion of the circuits of these embodiments, is sensitive to Single Event Upset and/or Single Event Transients.

A solid-state image sensor includes a pixel formed, upon forming a structure where a photoelectric conversion layer is laminated on a wiring layer constituting a pixel circuit, by forming at least the photoelectric conversion layer and a wiring layer bonding layer on a different substrate from a semiconductor substrate in which the wiring layer is formed, and by bonding the wiring layer bonding film of the different substrate and the wiring layer of the semiconductor substrate together.

The invention provides an OLED display panel and a manufacturing method thereof, and an OLED display device. The OLED display panel comprises a back plate, a substrate, a driving circuit layer, a light-emitting function layer and a packaging layer, wherein the substrate is arranged on the back plate; the driving circuit layer is arranged on the substrate; and the light-emitting function layer is arranged on the driving circuit layer, the packaging layer is arranged on the light-emitting function layer, and a sum of thicknesses of the back plate and the substrate in an electronic element setting area corresponding to an electronic element setting position is smaller than the sum of the thicknesses of the back plate and the substrate in other areas. In the invention, the thickness of at least one layer of the substrate and the back plate in the electronic element setting area is reduced so that light transmittance of the electronic element setting area is increased, an under-screen camera area is normally displayed, an under-screen camera is realized without digging a hole, a screen-to-body ratio is improved, and a technical problem that a display effect is influenced due to a fact that the under-screen camera area of the existing OLED display panel needs hole digging is solved.

An exemplary sensing circuit for sensing the current drawn by a target memory cell comprises a first transistor connected across a first node and a second node, a load connected across the second node and a third node, and a voltage boosting circuit coupled to a supply voltage, wherein the voltage boosting circuit supplies a voltage at the third node which is greater than the supply voltage.

A radio frequency circuit includes a multilayer substrate, series arm circuits in a first path connecting the input/output terminals (T1 and T2) on the multilayer substrate, a parallel arm circuit in a second path connecting a node on the first path and a ground, a wiring A on the multilayer substrate connected to the input/output terminal (T1) as a part of the first path, a wiring B on the multilayer substrate connected to the input/output terminal (T2) as a part of the first path, and a wiring C on the multilayer substrate as a part of the second path. The parallel arm circuit includes an impedance variable circuit, the wiring A and the wiring B in a layer different from the multilayer substrate. When viewed in a plan view, the wiring C does not overlap with the wiring A and the wiring B.

The invention relates to an intelligent power supply device for a low-temperature etching-free iron plating process, which is characterized in that three-phase alternating current supplies power for a silicon controlled rectifying circuit; an input end of the silicon controlled rectifying circuit is connected with a signal output end of a pulse signal generator; an output end of the silicon controlled rectifying circuit is connected with low-temperature iron plating loads; and signal output ends of a synchronizing signal generator and a PLC (programmable logic controller) are respectively connected with a signal input end of the pulse signal generator. The invention also discloses a power supply method of the intelligent power supply device. Phase-shifting control signals generated by the PLC are used for controlling the pulse signal generator, thus adjusting AC (alternating-current) and DC (direct-current) amplitudes; and AC and DC switching signals generated by the PLC are used for mutually switching between AC output and DC output. The power supply device is used for setting output duration of DC signals and output duration of AC signals, can be controlled automatically without manual operations, and is strong in reliability of power supply and convenient to operate.

The invention provides a silicon-controlled rectifier and a manufacturing method. The silicon-controlled rectifier comprises a semiconductor substrate; a first N trap, a P trap and a second N trap which are generated in the semiconductor substrate and sequentially and adjacently arranged; a first high-concentration P-type doping and a first high-concentration N-type doping which are located at theupper part of the first N trap; a second high-concentration N-type doping and a second high-concentration P-type doping which are located at the upper part of the second N trap; and a third high-concentration P-type doping which is positioned at the upper part of the P trap. The first high-concentration P-type doping and the first high-concentration N-type doping are connected to form a first device electrode; and the second high-concentration N-type doping and the second high-concentration P-type doping are connected to form a second device electrode. According to the designed and manufactured silicon-controlled rectifier, the structural characteristics of the device are symmetrically distributed, a PNPN channel can be formed when the high-voltage input and output end of positive high voltage or the high-voltage input and output end ofnegative high voltage are connected on first device pole (or the second device pole) without the conduction condition in any direction, and the bidirectional anti-static protection function of the positive high voltage and the negative high voltage can be achieved while circuit application is implemented.

The embodiment of the invention provides an over-current detection and protection circuit for a power MOS transistor, and a power MOS transistor assembly. The over-current detection and protection circuit comprises a current sampling module and a grid control module. The current sampling module is suitable for sampling current flowing through the source electrode of the power MOS tube. The input end of the grid control module is coupled with the source electrode of the power MOS tube, and the output end of the grid control module is coupled with the grid electrode of the power MOS tube to provide grid driving voltage for the power MOS tube, so that the current does not exceed the current threshold value of the power MOS tube. Therefore, the current flowing through the power MOS tube does not have overcurrent, and the current threshold value is accurately calculated without deviation of the current threshold value, so that advanced protection or protection failure of the power MOS tube caused by the deviation can be avoided.

A bit line resetting signal is supplied to the gate of an nMOS transistor (or a precharge circuit) which connects a bit line with a precharge voltage line. The high-level voltage of the bit line resetting signal is retained at a first voltage during the precharge operation after a refresh operation, and is retained at a second voltage higher than the first voltage during the precharge operation after an access operation. In the precharge operation after the refresh operation, therefore, the second voltage is not used so that the current consumption of the generating circuit of the second voltage is reduced. Thus, it is possible to reduce the current consumption (or the standby current) during the standby period for which the internal refresh requests continuously occur.

A circuit and method for test mode entry of a semiconductor memory device are provided. In a method of entering a semiconductor memory device into a test mode, an internal clock is generated in response to an external clock when a first condition is satisfied. An address combination signal is generated based on a first address combination and the internal clock. The semiconductor memory device is entered into the test mode using the internal clock and the address combination signal.

The invention relates to a booster circuit and method for improving the programming accuracy of an EEPROM. The booster circuit comprises a register, an MOS tube switch array, a reference source, a charge pump and the EEPROM. The booster circuit fully utilizes the characteristic that the data of the EEPROM memorizer can be saved for enough long time when a chip is powered down to specially mark out a small part of an EEPROM storage area as a special correction area. The booster circuit has the advantages that a common register is firstly used for adjusting the accuracy of the booster circuit in a chip testing mode, the EEPROM can perform normal programming and stores the data in the register in the EEPROM special correction area when an accurate booster circuit voltage value is obtained. The booster circuit occupies small chip area and is low in cost. In addition, the register in the circuit can be repeated scanned, the digit can be corrected to be higher, and the correction accuracy is high.

The invention provides a power switch circuit system comprising an intelligent power module which comprises an upper bridge arm driving chip, a lower bridge arm driving chip and a power switch devicecomposed of a plurality of insulated gate bipolar transistors (IGBTs) located on a plurality of bridge arms, wherein the IGBT on each bridge arm comprises an upper bridge arm IGBT connected with the upper bridge arm driving chip, and a lower bridge arm IGBT connected with the lower bridge arm driving chip; a protection circuit externally connected to the output end of the upper bridge arm drivingchip and the output end of the lower bridge arm driving chip in the intelligent power module, wherein the protection circuit comprises a voltage stabilization protection circuit used for stabilizing the voltage of the output ends within a set voltage range; and/or a current stabilization protection circuit used for bypassing the displacement current of the output end to a ground wire. According tothe invention, the voltage stabilization protection circuit and/or the current stabilization protection circuit can be connected in the IPM module, the grid oscillation and parasitic conduction are reduced, and the utilization rate and reliability of the device are improved.

The invention belongs to the ultrasonic wave field, particularly relates to an ultrasonic ranging system based on a single-chip microcomputer and aims to realize properties of strong directivity and small-amount energy consumption. The ultrasonic ranging system comprises a pulse generator and a driver. The ultrasonic ranging system is characterized in that the pulse generator and the driver are respectively connected with the single-chip microcomputer, the single-chip microcomputer is further connected with a display and an automatic gain module, the single-chip microcomputer is connected with a callback discriminator through a shaping circuit, and the single-chip microcomputer is further connected with a conversion module.

The invention discloses a circuit for reducing the power consumption of a TOSA. The circuit comprises a DC-DC power module. The feedback end of the DC-DC power module is connected with the ground through a third resistor and connected with a microcontroller through a second resistor. A first resistor is connected between the output end of the DC-DC power module and the second resistor in series. The output end of the DC-DC power module is connected with a collector of a triode. A base electrode of the triode is connected with an APC circuit, and an emitting electrode of the triode is connected with a laser diode of the TOSA through a fourth resistor. The microcontroller is connected with the two ends of the fourth resistor in parallel and used for monitoring the difference of the voltage across the two ends of the fourth resistor, and the output voltage of the DC-DC power module is gradually reduced according to the difference of the voltage. According to the circuit for reducing the power consumption of the TOSA, due to the fact that the output voltage of the DC-DC direct-current power module is gradually reduced, under the condition that the TOSA works stably, the power consumption of the TOSA is effectively reduced.

The invention relates to a self-induction-type liquid crystal display stripping structure which comprises a stripping platform. An electric heating element is arranged on the stripping platform, a bonding layer softening detecting device is arranged on the stripping platform, and the electric heating element and the bonding layer softening detecting device are in circuit connection with a main control circuit. In the heating process, after softening of a bonding layer between an IC and a liquid crystal reaches the stripping force (the force can be adjusted according to different products) set by the stripping structure, the stripping structure can conduct automatic stripping, influences on products due to the fact that forced stripping is conducted at the time earlier than stripping time stripping is too late and heating is too long can be avoided, the product percent of pass can be improved, and the self-induction-type liquid crystal display stripping structure is applicable to different products.