5 results about "Memory cell" patented technology

The present invention proposes a static random-access memory device (SRAM). The static random-access memory device is composed of two P-channel gates of loading transistor, two N-channel gates of driving transistor and two N-channel gates of accessing transistor in a memory cell. A dummy gate is disposed adjacent to the N-channel gate of accessing transistor with a bit line node disposed therebetween, wherein the dummy gate is electrically connected to a ground voltage through a metal layer.

The invention discloses a method for skipping the functional software branches of a vehicle-mounted controller. The method comprises the steps of respectively placing a hardware test software and a control software in the different sections of a flash, so as to share a same RAM (Random Access Memory) memory unit in a time-sharing way under the premise that addresses are not conflicted; setting a group of skip combined signal input values as a condition for switching different function softwares, after the vehicle-mounted controller is electrified, reading the skip combined signal input values in a skip procedure, and then skipping to either the hardware test software or the control software according to the skip combined signal input values; and synthesizing the output files of the skipping procedure, the hardware test hardware and the control software to a target production file, and burning the target production file into the vehicle-mounted controller in the process of manufacturing. According to the method, the skipping of the function software branches (the hardware test software and the control software) can be realized in the inspection and evaluation of the vehicle-mounted controller hardware and the functional verification of the control software, so that the additional work caused by frequently burning the softwares can be reduced, and the production efficiency can be improved.

Each of memory blocks of a nonvolatile memory device includes a memory cell region including first metal pads, first memory cells of a first portion of pillar, and second memory cells of a second portion of the pillar, and a peripheral circuit region including second metal pads, a row decoder, and a page buffer. When performing program operations based on consecutive addresses at a memory block selected from the memory blocks, the nonvolatile memory device sequentially completes first program operations of non-adjacent memory cells not adjacent to a boundary of the first portion and the second portion from among the first and second memory cells and then completes a second program operation of an adjacent memory cell adjacent to the boundary. The peripheral circuit region is vertically connected to the memory cell region by the first metal pads and the second metal pads directly.

A memory device includes a memory array and a frequency-to-voltage converter. The memory array includes a plurality of memory cells arranged in rows and columns, and gates of the memory cells in the same row are coupled to each other and connected to a word line. The frequency-to-voltage converter coupled between the word line and a clock signal source outside the memory device receives a clock signal, and correspondingly outputs different voltages to the word line in accordance with the frequency of the clock signal.