300results about "Semiconductor/solid-state device details" patented technology

An interposer for use in an external lead or land pattern semiconductor package. The interposer includes an interposer body which is molded from a dielectric material. The interposer body defines opposed top and bottom surfaces, an outer peripheral edge, and an inner peripheral edge. Embedded within the interposer body is a die pad which itself defines opposed top and bottom surfaces and a peripheral edge. The bottom surface of the die pad is exposed in and substantially flush with the bottom surface of the interposer body, with the inner peripheral edge of the interposer body and the top surface of the die pad collectively defining a cavity of the interposer. A plurality of electrically conductive interposer leads are embedded within the top surface of the interposer body and at least partially exposed therein. The interposer body forms a nonconductive barrier between each of the interposer leads and between the interposer leads and the die pad.

A semiconductor device includes a semiconductor substrate including a main surface; a plurality of first interconnections formed in a capacitance forming region defined on the main surface and extending in a predetermined direction; a plurality of second interconnections each adjacent to the first interconnection located at an edge of the capacitance forming region, extending in the predetermined direction, and having a fixed potential; and an insulating layer formed on the main surface and filling in between each of the first interconnections and between the first interconnection and the second interconnection adjacent to each other. The first interconnections and the second interconnections are located at substantially equal intervals in a plane parallel to the main surface, and located to align in a direction substantially perpendicular to the predetermined direction.

In the case where high speed differential signals are transmitted in differential transmission lines through via holes with open-stubs, signal waveforms are distorted due to impedance mismatch in the open-stubs of the via holes, thus causing jitter, which has become an issue of high speed signals. For differential transmission lines that pass through via holes with open-stubs, a degree of coupling of the lines is decreased while the differential characteristic impedance is made constant. Thereby, the effects of backward cross talk noise caused by the coupling can be minimized, and thus jitter can be suppressed.

An image pickup device is disclosed that has little deformation caused by thermal expansion of a transparent resin for sealing an image pickup element. The image pickup device includes an image pickup element having a light receiving surface, a micro-lens for condensing incident light to the image pickup element, a first transparent plate disposed on the light receiving surface of the image pickup element with the micro-lens in between, a transparent resin that seals the image pickup element and the first transparent plate, and a second transparent plate disposed on the transparent resin to face the first transparent plate.

A semiconductor package has a printed circuit board, an integrated circuit chip on the printed circuit board with an exposed semiconductor die, and a rigid structure secured to the printed circuit board and enclosing the exposed semiconductor die. The exposed surface of the semiconductor die placed is in thermal contact with an inner surface of the rigid structure with a compressible material.

A multilayer wiring board capable of feeding sufficient electric power to a circuit element, such as an IC chip. In one embodiment of the present invention, a multilayer wiring board is comprised of: a core board; a build up layer disposed on an upper surface of the core board; a build up layer disposed on a lower surface of the core board; and a power supply structure embedded in a through hole penetrating the core board and the build up layers. The power supply structure is comprised of: a conductive metal rod made of copper as a main material; a conductive metal tube made of copper as a main material and provided coaxially with the conductive metal rod; and an insulating material filling a gap between the conductive metal rod and the conductive metal tube.

A contact structure includes a permanent antireflection coating formed on a substrate having contact pads. A patterned dielectric layer is formed on the antireflective coating. The patterned dielectric layer and the permanent antireflective coating form openings. The openings correspond with locations of the contact pads. Contact structures are formed in the openings to make electrical contact with the contacts pads such that the patterned dielectric layer and the permanent antireflective coating each have a conductively filled region forming the contact structures.

A stack of semiconductor chips includes a substrate or an interposer board comprising conductor structures for electrical connection of the stack and a first chip. The first chip includes an active side with peripherally arranged bonding pads and is mounted face-up on the substrate or the interposer board. The stack beyond includes at least a further chip with peripherally arranged bonding pads on its active side. The back side and at least two chip edges of the further chip are embedded by a mold cap providing a protuberance on the back side of the chip. The protuberance forms a planar surface extending substantially parallel and with a distance to the back side of the chip. The further chip is attached face-up to the active side of the first chip by an adhesive applied between the protuberance and the first chip so that the protuberance is inserted between both chips to provide a gap there. The protuberance has at least one linear dimension that is smaller than a linear dimension of the subjacent chip.

A heat dissipation element which can be shaped as a flat plate for transfer of heat to the opposite side of a mounting channel in a chassis for holding circuit cards. Circuit cards are typically held in place in channels in a chassis by an expansion type retention device. The circuit cards also include a heat frame for collecting the heat produced by the card components and channeling the heat from the card through the heat frame to the chassis. The retention device presses the heat frame in to thermal contact with one side of the channel. The heat dissipation plate is held in thermal contact with the other side of the channel, providing a second additional heat path to channel heat away from individual components, the circuit card and/or the heat frame.

A capacitor structure including a plurality of conductive layers, a dielectric layer and a plurality of contacts is disclosed. The conductive layers are stacked, and each conductive layer has a first conductive pattern and a second conductive pattern. The dielectric layer is disposed between the first conductive pattern and the second conductive pattern and between two adjacent conductive layers. The contacts are disposed in the dielectric layer, and electrically connected to the first conductive patterns in two adjacent conductive layers and electrically connected to the second conductive patterns in two adjacent conductive layers. Wherein, the contact electrically connecting to the first conductive patterns in two adjacent conducive layers is a first strip contact, which extends between the first conductive patterns in two adjacent conductive layers, and the boundary of the first strip contact is located within the boundary of the first conductive pattern.

A thermal management device for the removal of thermal energy useful for, inter alia, electronic devices or other components.

A through-silicon via stack package contains package units. Each package unit includes a semiconductor chip; a through-silicon via formed in the semiconductor chip; a first metal line formed on an upper surface and contacting a portion of a top surface of the through-silicon via; and a second metal line formed on a lower surface of the semiconductor chip and contacting a second portion of a lower surface of the through-silicon via. When package units are stacked, the second metal line formed on the lower surface of the top package unit and the first metal line formed on the upper surface of the bottom package unit are brought into contact with the upper surface of the through-silicon via of the bottom package unit and the lower surface of the through-silicon via of the top package unit, respectively. The stack package is lightweight and compact, and can form excellent electrical connections.

An electronic device with integrated discrete components, including a wafer including cavities that can receive the components, an active face of the components being in a same plane as a face of the receiving wafer, and a material for laterally coating the components in the cavities.

The invention relates to an electronic device with integrated discrete components (4), including:

• • a wafer (2), a so-called receiving wafer, said wafer having cavities (5, 5′) containing said components, the active face (10) of which is in a same plane as a face (8) of the receiving wafer,
  • a material (6) for laterally coating the components in the cavities.

An integrated circuit structure includes a semiconductor substrate; a dielectric layer over the semiconductor substrate; a conductive wiring in the dielectric layer; and a metal carbide cap layer over the conductive wiring.

A semiconductor carrier film includes (i) a base film having insulating property, (ii) a barrier layer provided on the base film, the barrier layer including nickel-chrome alloy as a main component, and (iii) a wire layer provided on the barrier layer, the wire layer being made of conductive material including copper, and a ratio of chrome in the barrier layer is 15% to 50% by weight. A semiconductor device is formed by bonding a semiconductor element to the wire layer. The semiconductor carrier film and the semiconductor device are suitable for attaining finer pitches and higher outputs, because insulating resistance between adjacent terminals is less likely to deteriorate then in conventional art even in the environment of high temperature and moisture.

A semiconductor device includes at least three or more wiring layers stacked in an interlayer insulating film on a semiconductor substrate, a seal ring provided at the outer periphery of a chip region of the semiconductor substrate and a chip strength reinforcement provided in part of the chip region near the seal ring. The chip strength reinforcement is made of a plurality of dummy wiring structures and each of the plurality of dummy wiring structures is formed to extend across and within two or more of the wiring layers including one or none of the bottommost wiring layer and the topmost wiring layer using a via portion.

A system and method of assembling a ball grid array (BGA) package with IC die support is described. A stiffener is attached to a substrate that includes a centrally located opening with an integrated circuit (IC) die support structure removably held therein. An IC die is mounted to a central region of the stiffener. Further assembly process steps may be performed on the BGA package with IC die support. The IC die support structure is removed from the centrally located opening. In aspects of the invention, the IC die support structure is removably held in the opening by an adhesive tape or by one or more substrate tabs.

A modular motor controller family comprises a housing. Solid state switches are selected from one of plural switch sizes for controlling a desired voltage and current range. The switches are mounted in the housing for connection between an AC line and motor terminals for controlling application of AC power to the motor. A logic circuit board is mounted in the housing including logic circuitry for commanding operation of the solid state switches independent of the selected switch size. An interface circuit board selected from one of plural configurations is mounted in the housing and includes interface circuitry connected between the logic circuitry and the solid state switches. The interface circuitry is selected to interface with the selected switch size according to the desired voltage and current range.

Carbon-nanotube-based devices or nanowire-based devices are formed in multiple layers to obtain higher density of such devices. The layers may be all similar such as all carbon-nanotube-based transistors. Or they may be different, such as one layer with nanowire devices and another layer with nanotube devices. Or some layers such as the bottom layer may be based on silicon devices and another layer with nanotube devices. Traditional interconnects and vias may be used to connect layers and electrodes, or nanoscale materials such as nanotubes or nanowires may be used as interconnects or vias.

The invention discloses a preparation method for a photolithographic alignment mark. The method is used for preparing the photolithographic alignment mark on a silicon substrate and comprises the following steps: preparing an oxidation layer on the silicon substrate; carrying out the photolithography and development through photoresist and retaining the photoresist at the position of the photolithographic alignment mark; taking the formed photoresist pattern as a photolithographic masking plate so as to etch and expose the oxidation layer to the silicon surface, and finally removing the photoresist layer; and carrying out the silicon epitaxy growth to make the surface height of the epitaxial layer higher than that of the oxidation layer and form the photolithographic alignment mark. The preparation method avoids the problem of a fuzzy mark caused by the thickened epitaxial layer in the prior method for the photolithographic alignment mark based on ditch groove etching. Simultaneously, the method has the advantages of low manufacturing cost, simple process control, extended process capability window, and high alignment accuracy. The method is applied to the manufacturing of integrated circuits.

The present invention is directed to a reversibly adhesive thermal interface material for electronic components and methods of making and using the same. More particularly, embodiments of the invention provide thermal interface materials that include a thermally-reversible adhesive, and a thermally conductive and electrically non-conductive filler, where the thermal interface material is characterized by a thermal conductivity of 0.2 W/m-K or more and an electrical resistivity of 9×10¹¹ ohm-cm or more.