64 results about "Dielectric layer" patented technology

In a first structure, a metal gate portion may be laterally recessed from a substantially vertical surface of a gate conductor thereabove. A cavity is formed between the metal gate portion and a gate spacer. In a second structure, a disposable gate portion is removed after laterally recessing a metal gate portion therebeneath and forming a dielectric layer having a surface coplanar with a top surface of the disposable gate portion. (We have to include the inner spacer without a metal recess). An inner gate spacer is formed over a periphery of the metal gate portion provide a reduced overlap capacitance. In a third structure, a thin dielectric layer is employed to form a cavity next to the metal gate portion in conjunction with the inner gate spacer to provide reduced overlap capacitance.

A capacitor structure including a plurality of conductive layers, a dielectric layer and a plurality of contacts is disclosed. The conductive layers are stacked, and each conductive layer has a first conductive pattern and a second conductive pattern. The dielectric layer is disposed between the first conductive pattern and the second conductive pattern and between two adjacent conductive layers. The contacts are disposed in the dielectric layer, and electrically connected to the first conductive patterns in two adjacent conductive layers and electrically connected to the second conductive patterns in two adjacent conductive layers. Wherein, the contact electrically connecting to the first conductive patterns in two adjacent conducive layers is a first strip contact, which extends between the first conductive patterns in two adjacent conductive layers, and the boundary of the first strip contact is located within the boundary of the first conductive pattern.

The invention relates to an amorphous silicon image sensor with a storage capacitor structure, comprising a plurality of pixel units. Each pixel unit comprises a grid wiring, a first insulating layer, an active layer, a data wiring, a second insulating layer, a storage capacitor, a photosensitive diode, a passivation layer and a bias voltage wire, wherein the storage capacitor is arranged below the photosensitive diode; a lower electrode of the storage capacitor is formed on a glass substrate or the first insulating layer, and an upper electrode of the storage capacitor is formed on a dielectric layer and connected with a source electrode; a first electrode of the photosensitive diode is in co-electrode with the upper electrode of the storage capacitor; and a second electrode of the photosensitive diode is conductive with the lower electrode of the storage capacitor and the bias voltage wire. By means of the amorphous silicon image sensor disclosed by the invention, the charge storagecapacity of the pixel units is increased under the condition of not enlarging or reducing pixel dimensions by arranging the storage capacitor below the photosensitive diode, and therefore the purposeof enhancing the signal dynamic range of a thin film transistor matrix panel under the precondition of not losing the resolution ratio of the thin film transistor matrix panel is achieved.

A capacitive liquid level detector for detecting a liquid level of a liquid in a receptacle, the liquid being conductive, the detector comprising: a capacitor with a first plate having a fixed size and being insulated from the liquid, and a second plate being formed by the liquid itself, its size being variable depending on the liquid level inside said receptacle, wherein a thin film dielectric layer is formed on the surface of the first plate and located between the first plate and the second plate, the first plate with the thin film dielectric layer formed on its surface is arranged such that it covers an open part of the outer wall of the receptacle, the first plate with the thin film dielectric layer formed on its surface is attached to the receptacle by sealing means in order to seal the receptacle against liquid leakage.

A master having a substrate including displaying units and an ESD protection structure including an adjacent first region and a second region is provided. The displaying units have a predetermined-cutting region therebetween. Each displaying unit includes a peripheral circuit region and a display region having pixels. The ESD protection structure disposed on the predetermined-cutting region, located in the peripheral circuit region, and connecting the display region includes a first patterned conductive layer disposed on the first region and having an end away from the predetermined-cutting region, a first patterned dielectric layer disposed on the first patterned conductive layer and the substrate and having a first opening exposing a portion of the first patterned conductive layer, a patterned transparent conductive layer disposed corresponding to the predetermined-cutting region and connecting the first patterned conductive layer, and a second patterned dielectric layer covering the patterned transparent conductive layer and the substrate.

The invention suppresses the occurrence of cracks in a dielectric layer, and improve yield during manufacture of a dielectric device. A dielectric device includes a substrate, a base electrode and a dielectric layer. The base electrode is fixed on the substrate. The base electrode is formed such that a surface of a base electrode edge part has an inclined part. The dielectric layer is fixed on a substrate surface so as to cover the base electrode. The dielectric layer is formed by annealing a deposited layer obtained by spraying a powdered dielectric on the substrate surface. Therefore, a triple point adjacent part, which is a part of the dielectric layer opposite the base electrode edge part, is formed so as to have a dense structure in the same way as other parts.

The invention provides a method for manufacturing a flash memory. The method comprises the following steps of: providing a substrate, wherein a plurality of isolation structures are arranged on the substrate, and a dielectric layer and a floating gate are arranged on the substrate among the isolation structures; forming a mask layer on the substrate to cover the isolation structures in a peripheral area and the isolation structures which are positioned in a memory area and are adjacent to the peripheral area; removing one part of the isolation structures in the memory area by taking the mask layer as a mask, so that the first height difference between the surfaces of the isolation structures in the peripheral area and the surface of the dielectric layer and between the surfaces of the isolation structures which are positioned in the memory area and are adjacent to the peripheral area and the surface of the dielectric layer exists, and the second height difference which is less than first height difference exists between the surfaces of the rest isolation structures in the memory area and the surface of the dielectric layer; removing the mask layer; forming a gate dielectric layer on the substrate; and forming a conductor layer on the substrate. The flash memory manufactured by the method has high-grid coupling efficiency and excellent electrical property.

The present invention relates to a non-volatile ferroelectric memory device including a semiconductor active layer, a plurality of memory cells connected in series on the semiconductor active layer, and a control circuit for performing a read operation and a program operation on the selected memory cell among the plurality of memory cells, each of the memory cells comprising a para-dielectric layer on the semiconductor active layer; a dielectric stack including a ferroelectric layer stacked on the para-dielectric layer and a charge trap site for generating a negative capacitance effect of the ferroelectric layer by charges disposed and trapped at an interface between the ferroelectric layer and the para-dielectric layer; and a control gate electrode on the ferroelectric layer.

An apparatus for treating a substrate may include a process chamber. The process chamber may include a reaction space and an opening portion for receiving the substrate into the reaction space. The apparatus may further include a dielectric layer. The apparatus may further include a plurality of support elements disposed on the dielectric layer and configured to contact a bottom surface of the substrate for supporting the substrate. The plurality of support elements may include a first support element and a second support element immediately neighboring the first support element.

A technique for achieving both discharge voltage reduction and discharge stabilization in a PDP and the like is provided. This PDP manufacturing method includes, for a structure of a front plate structure (11) to be exposed to a discharge space (30) to be filled with a discharge gas, a step of forming a first layer (4) having an effect of discharge protective layer on a dielectric layer (3), a step of forming a second layer (5) for protecting the first layer on the first layer, and a step of forming a third layer (6) of a powder for discharge stabilization to be exposed to the discharge space (30), the steps being performed in vacuum manufacturing process. And, the structure is made such that a surface of the first layer is exposed to the discharge space (30) by a step of removing the second layer by an aging discharge in the discharge space (30).

A process for forming a void-free dielectric layer is disclosed in which adjoining gate film stacks are formed on a semiconductor substrate. Each gate film stack includes a silicide layer and a hard mask that overlies the silicide layer. A first selective etch is performed so as to reduce the width of the hard mask on each of the gate film stacks, exposing portions of the top surface of the silicide layer. A second selective etch is then performed to reduce the width of the silicide layer. Spacers are then formed on opposite sides of each of the gate film stacks, and a dielectric film is formed that extends over the gate film stacks. By reducing the width of the hard mask layer and the silicide layer, gate film stacks are obtained that have reduced width near the top of each gate film stack, preventing voids from forming in the dielectric film.

The invention discloses a rectangular waveguide covered with a dielectric layer in the technical field of communication cables. A waveguide structurally comprises the rectangular waveguide and the dielectric layer, wherein the dielectric layer is arranged on the rectangular waveguide; the wall of the rectangular waveguide is provided with a slot array formed by a plurality of slots at uniform intervals along the axis direction. The dielectric layer is added on the rectangular slot waveguide, and the electric field intensity of a working area on the surface of the rectangular slot waveguide is obviously improved; the divergence degree of an electromagnetic field is reduced; meanwhile, proper thickness and dielectric constant of the dielectric layer are selected, and the radiation intensity of a working area of a rectangular slot waveguide cable can be controlled. The rectangular waveguide can be applied to a communications based train control (CBTC) railway mobile communication system, the near field intensity on the upper side of the rectangular slot waveguide is improved, the space convergence of an electric field is improved, and the system has the best working condition.

The invention provides a nanotube memory structure and a preparation method thereof. The nanotube memory structure comprises the components of a semiconductor substrate with a heavily doped epitaxiallayer on the surface; a first isolating dielectric layer, a ground selecting gate electrode layer, a bit line gate electrode layer, a string selecting gate electrode layer, and multiple second isolating dielectric layers among the ground selecting gate electrode layer, the bit line gate electrode layer and the string selecting gate electrode layer, wherein the first isolating dielectric layer, theground selecting gate electrode layer, the bit line gate electrode layer, the string selecting gate electrode layer and the multiple second isolating dielectric layers are arranged on the semiconductor substrate; a semiconductor channel which penetrates through the ground selecting gate electrode layer, the bit line gate electrode layer and the string selecting gate electrode layer; and a gate electrode dielectric layer which packages the sidewall of the semiconductor channel, wherein the semiconductor channel is a semiconductor nanotube on the heavily doped epitaxial layer. According to thememory structure, the semiconductor nanotube which epitaxially grows on the heavily doped epitaxial layer is used as the vertical channel; and compared with an existing vertical channel type NAND structure, the nanotube memory structure has advantages of further simplified device structure, easy controlling for the preparation process, and high yield rate of products.

An improved smoothing layer for use with a thick film dielectric layer, and improved composite thick film dielectric structure is provided. The smoothing layer is a piezoelectric or ferroelectric material that has a reduced amount of defects. The smoothing layer is formed by the addition of surfactant to a sol gel or metal organic solution of organo metallic precursor compounds. The composite thick film dielectric structure comprises a thick film dielectric composition having a PZT smoothing layer thereon, the smoothing layer being made by a process incorporating surfactant. Both the smoothing layer and the composite thick film dielectric structure are for use in electroluminescent displays.

A composite electronic component includes a composite body in which a multilayer ceramic capacitor and a ceramic chip are coupled to each other, the multilayer ceramic capacitor including a first ceramic body in which a plurality of dielectric layers and internal electrodes disposed to face each other with respective dielectric layers interposed therebetween are stacked, and first and second external electrodes disposed on both end portions of the first ceramic body, and the ceramic chip being disposed on a lower portion of the multilayer ceramic capacitor and formed of a ceramic material having substantially no piezoelectric property, wherein a ratio (T/L) of thickness (T) of the ceramic chip to length (L) of the multilayer ceramic capacitor is selected to minimize vibration of the ceramic chip.