20 results about "Flash memory" patented technology

When a shutter button of a digital camera is pressed, a picture signal fetched from a CCD is converted to a digital signal and compressed and written into a nonvolatile memory means like a flash memory card as a picture file which can be identified uniquely. By turning on a reproduction switch, a picture file is read out from the nonvolatile memory means, the compressed data is expanded and converted to an analog signal, and the converted picture is displayed on a liquid crystal display. By pressing a display feed key, another picture file is read out and displayed. A user can produce a control file for controlling print processing, display processing, transmission processing and the like for the picture file by selecting a particular picture file using an operation key. The nonvolatile memory means can be removed. By mounting this memory means on a printer unit, display unit or picture transmission unit, the digital camera also can be used during print, display or transmission of the picture. If multi-screen print is carried out on the printer unit, a vertical direction of each picture is unified. Further, upon reprint operation for multiple order persons, sorting work after the print is facilitated by providing with an identification means for identifying each order person.

A process and a memory architecture is based on “vertical” pages, and support byte by byte erasure. A byte within a “vertical” page is erased, and then other bytes within the “vertical” page sharing bit lines with the erased byte, are subjected to a program verify operation after exposure to the stress caused by the erase process. The other bytes in the page are re-programmed to recover the data if they fail verify. Therefore, byte erase is executed without the erase/re-program cycling, and only memory cells within the same vertical page as the erased byte, which suffer stress from the erase potentials on the shared bit lines sufficient to shift their thresholds out of range, are re-programmed.

A method, system and memory controller are provided for implementing ECC (Error Correction Codes) control to provide enhanced endurance and data retention of flash memories. The memory controller includes a VT (threshold voltage) monitor to determine VT degradation of cells and blocks; the VT monitor configured to store information about the determined VT degradation; a first ECC engine having a first level of ECC capability; a second ECC engine having a second level of ECC capability, the second level higher than the first level, the second ECC engine having a longer latency than the first ECC engine; a logic to issue a read request to a particular cell/block, and, using the determined VT degradation, use the first ECC engine if the determined VT degradation is less than a threshold and to use the second ECC engine if the determined VT degradation is above the threshold.

A flash memory device including: a memory cell array; a signal generator inputting a first data fetch signal and outputting a second data fetch signal; and an output buffer circuit configured to output data from the memory cell array in sync with rising and falling edges of the second data fetch signal, wherein second data fetch signal is output along with data output from the output buffer circuit.

The invention relates to a block access-based flash reading and writing method. The method comprises the following steps of: 1, scanning physical blocks of the flash to acquire corresponding page status tables of the physical blocks; 2, acquiring a partition physical block numbering table; 3, acquiring a partition capacity table of partitions according to the number of partition physical blocks and the number of corresponding effective pages; 4, determining the serial number of the partition accessed by an application layer and the offset in the partition according to the partition capacity table; 5, acquiring the virtual block number and virtual page number of the partition through the offset according to the number of effective pages of the physical blocks in the partition; and 6, acquiring the serial numbers of the physical blocks according to the virtual block number along with the partition physical block numbering table, and acquiring the physical page numbers of the effective pages according to the virtual page number along with the page status table of the physical block. By mapping the physical layers with ineffective pages into a continuous linear storage medium, the effective capacity of the storage medium is maximally extended.

The invention provides a method for manufacturing a flash memory. The method comprises the following steps of: providing a substrate, wherein a plurality of isolation structures are arranged on the substrate, and a dielectric layer and a floating gate are arranged on the substrate among the isolation structures; forming a mask layer on the substrate to cover the isolation structures in a peripheral area and the isolation structures which are positioned in a memory area and are adjacent to the peripheral area; removing one part of the isolation structures in the memory area by taking the mask layer as a mask, so that the first height difference between the surfaces of the isolation structures in the peripheral area and the surface of the dielectric layer and between the surfaces of the isolation structures which are positioned in the memory area and are adjacent to the peripheral area and the surface of the dielectric layer exists, and the second height difference which is less than first height difference exists between the surfaces of the rest isolation structures in the memory area and the surface of the dielectric layer; removing the mask layer; forming a gate dielectric layer on the substrate; and forming a conductor layer on the substrate. The flash memory manufactured by the method has high-grid coupling efficiency and excellent electrical property.

An image forming apparatus which has a hibernation function and is capable of selecting a suitable startup method even in a case where device connection states are different at power-off and at next startup. A hibernation image created based on data stored in a memory of the image forming apparatus and a first device connection state indicative of whether the device is connected to the image forming apparatus are stored in a flash disk. After that, when power to the image forming apparatus is turned off and the power is turned on again, a second device connection state indicative of whether the device is connected to the image forming apparatus is obtained. When the first and second connection states are different, the image forming apparatus is started without using the hibernation image, and when they are the same, the image forming apparatus is started using the hibernation image.

A control terminal section CON and an address terminal section ADDR of a test apparatus are respectively connected to those of a flash memory. A first to an (n−1) -th input and output terminal of the test apparatus are connected to data terminals of the flash memory. Further, an n-th and an (n+1)-th input and output terminal of the test apparatus are connected to a multifunctional terminal of the flash memory. The (n+1)-th input and output terminal is established as a dedicated terminal to receive data supplied to the test apparatus. The first to the n-th input and output terminal of the test apparatus are used to output the writing data to the flash memory, while the (n+1)-th input and output terminal is used to detect the completion signal output from the flash memory.

A system and method for performing sleep state enhancements in a computing device using firmware and NVDIMMs that include DRAM and flash memory is discussed. The flash-backed DRAM covers all of platform memory. All writes to DRAM during system operation are propagated to the flash. Sleep state requests trigger a System Management Interrupt and a firmware a SMI handler handles the sleep state request so as to enable power savings during the sleep state and facilitate faster resume times when exiting the sleep state.

The invention provides a flash memory device and a formation method thereof. The flash memory device comprises a semiconductor substrate, a plurality of floating gates, control gate dielectric layers, control gates, and selection gates, wherein the semiconductor substrate comprises a plurality of first regions parallel to each other and second regions located at one ends of the first regions; the plurality of floating gates are located on the first regions of the semiconductor substrate, and a first opening is formed between the adjacent floating gates; the control gate dielectric layers are located on the sidewalls and the bottoms of the first opening and the surfaces of the floating gates; the control gates are located on the control gate dielectric layers to fully fill in the first openings; the selection gates are located on the second regions of the semiconductor substrates; the top surfaces of the selection gates are flush with the bottom surfaces of the control gates. The performance of the flash memory device is improved.

The invention discloses a processing method and device and electronic equipment, aiming at a storage part of the electronic equipment, such as a flash memory or a solid state disk, the storage part is divided into a high-frequency storage space and a low-frequency storage space, the size of the high-frequency storage space and the size of the low-frequency storage space of the storage part are adjusted in an execution cycle, the proportional relation between the high-frequency storage space and the low-frequency storage space is adjusted, and the storage data in the high-frequency storage space is adjusted, so that the data of the file needing high-frequency access in the next use period of the electronic equipment is located in the high-frequency storage space. The size of the high-frequency storage space and the size of the low-frequency storage space in the storage part can be dynamically adjusted according to actual needs, the content in the high-frequency storage space can be dynamically adjusted to be data needing high-frequency access, and therefore the balance of the access speed, storage space saving and the like is achieved.

The invention discloses a mine tunnel soil pressure acquisition system. The system comprises a plurality of pressure sensors, a multi-channel amplifier, a multi-channel A/D converter, a processor, a FLASH storage module, a wireless communication interface module and a wireless charging module; the plurality of pressure sensors are used for outputting a plurality of acquired pressure data signals to the multi-channel amplifier; the multi-channel amplifier is used for amplifying the plurality of pressure data signals and outputting the amplified pressure data signals to the multi-channel A/D converter; and the multi-channel A/D converter is used for converting the amplified pressure data signals into digital signals and outputting the digital signals to the processor; the processor is used for processing the digital signals, and outputting the processed pressure data to the FLASH storage module and the wireless communication interface module; the FLASH storage module is used for storingthe processed pressure data; the wireless communication interface module is used for outputting the processed pressure data to the outside; and the wireless charging module is used for charging the processor. With the system adopted, the work efficiency of pressure detection can be improved.