43results about "Memory adressing/allocation/relocation" patented technology

The present invention provides a method and apparatus for optimizing bus utilization while maintaining read and write coherence. More specifically the invention provides bus utilization optimization by prioritizing read transactions before write transactions, where there is no collision pending. When a collision pending is determined, then the read and write transactions are processed according to the age of the transaction(s) allowing for data coherency.

A storage virtualization computer system. The storage virtualization computer system comprises a host entity for issuing an IO request, a storage virtualization controller coupled to the host entity for executing IO operations in response to the IO request, and a at least one physical storage device, each coupled to the storage virtualization controller through a point-to-point serial-signal interconnect, for providing storage to the storage virtualization computer system through the storage virtualization controller. As an example, the point-to-point serial-signal interconnect can be a Serial ATA IO device interconnect.

In a computer system supporting execution of virtualization software and at least one instance of virtual system hardware, an interface is provided into the virtualization software to allow a program to directly define the access characteristics of its program data stored in physical memory. The technique includes providing data identifying memory pages and their access characteristics to the virtualization software which then derives the memory access characteristics from the specified data. Optionally, the program may also specify a pre-defined function to be performed upon the occurrence of a fault associated with access to an identified memory page. In this manner, programs operating both internal and external to the virtualization software can protect his memory pages, without intermediation by the operating system software.

A data element can be encoded into multiple encoded data elements using an encoding algorithm that includes an encoding function and one or more encoder constant. The encoded data elements can be organized into multiple pillars, each having a respective pillar number. Each of the pillars is sent to a different storage unit of a distributed storage network. To recover the original data element, the encoded data elements are retrieved from storage, and the encoder constant is recovered using multiple encoded data elements. Recovering the encoder constant allows the encoding algorithm originally used to encode the data elements to be determined, and used to recover the original data element. The security of the stored data is enhanced, because an encoded data element from a single pillar is insufficient to identify the encoder constant.

A method and system for allowing a processor or I/O master to address more system memory than physically exists are described. A Compressed Memory Management Unit (CMMU) may keep least recently used pages compressed, and most recently and/or frequently used pages uncompressed in physical memory. The CMMU translates system addresses into physical addresses, and may manage the compression and/or decompression of data at the physical addresses as required. The CMMU may provide data to be compressed or decompressed to a compression/decompression engine. In some embodiments, the data to be compressed or decompressed may be provided to a plurality of compression/decompression engines that may be configured to operate in parallel. The CMMU may pass the resulting physical address to the system memory controller to access the physical memory. A CMMU may be integrated in a processor, a system memory controller or elsewhere within the system.

Branch prediction logic is enhanced to provide a monitoring function for certain conditions which indicate that the use of separate BHTs and predicted target address cache would provide better results for branch prediction. The branch prediction logic responds to the occurrence of the monitored condition by logically splitting the BHTs and count cache so that half of the address space is allocated to a first thread and the second half is allocated to the next thread. Prediction-generated addresses that belong to the first thread are then directed to the half of the array that is allocated to that thread and prediction-generated addresses that belong to the second thread are directed to the next half of the array that is allocated to the second thread. In order to split the array, the highest order bit in the array is utilized to uniquely identify addresses of the first and the second threads.

A system and method to defragment a memory is disclosed. In a particular embodiment, a method includes loading data stored at a first physical memory address of a memory from the memory into a cache line of a data cache. The first physical memory address is mapped to a first virtual memory address. The method further includes initiating modification, at the data cache, of lookup information associated with the first virtual memory address so that the first virtual memory address corresponds to a second physical memory address of the memory. The method also includes modifying, at the data cache, information associated with the cache line to indicate that the cache line corresponds to the second physical memory address instead of the first physical memory address.

The present invention belongs to the field of named data networks and particularly relates to a named data network cache management system based on cache space division and content similarity and a management method. The named data network cache management system based on the cache space division and the content similarity comprises a cache space division module, a content similarity matching module, a dynamic area cache module and a dynamic cache replacement module. According to the management method, a cache space of a node is divided into a static area and a dynamic area, wherein the static area is used for storing primary content information of the node and the primary content information is updated only within Tupdate time, so that the storage time of the content is ensured and the cache hit rate of the node can be increased. Meanwhile, the cache content of the dynamic area is updated, so that the diversity of the content in a network is ensured.

A method to form one or more premigration aggregates comprising a plurality of least recently accessed virtual volumes disposed in an information storage medium. The method determines the number (R) of virtual volumes to remove from the information storage medium, selects the (R) least recently accessed virtual volumes, forms one or more premigration aggregates comprising those least recently accessed virtual volumes, and assigns each of the (R) selected virtual volumes to one of those premigration aggregates. The method establishes a minimum transfer size and determines if any of the premigration aggregates are larger than that minimum transfer size. The method writes to one or more physical volumes each of the premigrate aggregates that are larger than the minimum transfer size. Thereafter, the method removes from the information storage medium each of the premigration aggregates written to physical volumes.

A memory system comprises a storage device and a host. The host classifies pages stored in the storage device into a plurality of data groups according to properties of the pages, and transmits setup information regarding the classified data groups to the storage device.

A processor contains a move engine and mapping engine that transparently reconfigure physical memory to accomplish addition, subtraction, or replacement of a memory module. A mapping engine register stores FROM and TO real addresses that enable the engines to virtualize the physical address of the memory module being reconfigured and provide the reconfiguration in real-time through the use of hardware functionality and not software. Using the FROM and TO real addresses to select a source and a target, the move engine copies the contents of the memory module to be removed or reconfigured into the remaining or inserted memory module. Then, the real address associated with the reconfigured memory module is re-assigned to the memory module receiving the copied contents, thereby creating a virtualized physical mapping from the addressable real address space being utilized by the operating system into a virtual physical address space. During the process of moving the memory contents, the mapping engine maps Write memory requests addressed to the real address space currently associated with the reconfigured memory module to both the FROM and TO real address space. As will be appreciated, a memory module can be inserted, removed or replaced in physical memory without the operating system having to direct and control the reconfiguration of physical memory to accomplish the physical memory change.

The invention relates to a block access-based flash reading and writing method. The method comprises the following steps of: 1, scanning physical blocks of the flash to acquire corresponding page status tables of the physical blocks; 2, acquiring a partition physical block numbering table; 3, acquiring a partition capacity table of partitions according to the number of partition physical blocks and the number of corresponding effective pages; 4, determining the serial number of the partition accessed by an application layer and the offset in the partition according to the partition capacity table; 5, acquiring the virtual block number and virtual page number of the partition through the offset according to the number of effective pages of the physical blocks in the partition; and 6, acquiring the serial numbers of the physical blocks according to the virtual block number along with the partition physical block numbering table, and acquiring the physical page numbers of the effective pages according to the virtual page number along with the page status table of the physical block. By mapping the physical layers with ineffective pages into a continuous linear storage medium, the effective capacity of the storage medium is maximally extended.

The invention discloses a method for distributing hybrid memory, which is characterized by including the following steps: configuring the exclusive memory of a browser and the threshold value used for the memory of the web browser; judging whether the size of the memory applied by the browser exceeds the threshold value used by the browser memory; distributing the memory applied by the browser from the exclusive memory of the non browser in the system; and releasing the memory applied by the browser and enabling other modules to be reused. The invention also discloses a system and a browser for distributing hybrid memory. By utilizing the embodiment and hybrid memory distribution, not only the exclusive memory of the browser can be utilized for effective and economical memory management strategy, but also the memory pressure caused by the exclusive memory of the browser on the system can be avoided to the maximum degree, as a result, the memory waste of the browser caused by producing a large amount of memory fragments can be avoided, and the memory application speed is improved.

The invention discloses a system and method for achieving home gateway data communication based on a Linux shared memory and relates to the technical field of Linux data communication. The system comprises a shared memory mutual exclusion access unit, a shared memory data reading unit, a shared memory data writing unit and a data synchronization unit, wherein the shared memory mutual exclusion access unit comprises a critical zone mutual exclusion initialization subunit, a critical zone permission acquiring subunit and a deadlock reconstruction subunit, the critical zone mutual exclusion initialization subunit, the critical zone permission acquiring subunit and the deadlock reconstruction subunit are connected sequentially, the critical zone mutual exclusion initialization subunit is connected with the shared memory data reading unit and the shared memory data writing unit, the data synchronization unit comprises a signal installation subunit, a signal monitoring subunit and a signal sending subunit, the shared memory data writing unit is connected with the signal installation subunit, and the signal installation subunit is connected with the signal monitoring subunit and the signal sending subunit. According to the system and method for achieving home gateway data communication based on the Linux shared memory, data safety of service configuration amount multiple processes of a home gateway system can be guaranteed, efficient sharing access can be achieved, and convenience is brought to people.

The invention discloses a data processing method and system and electronic equipment. The method comprises the steps that a cached data read request initiated by at least one processor process to a data cache system is received, the data cache system comprises multiple kinds of cache elements, transmission rates and/or storage spaces of the cache elements are different, and different searching priorities are preset according to the transmission rate and the storage space of each cache element; the received cached data read request is responded, and the corresponding cache data is searched fromthe cache elements according to the search priorities in a sequence of from high to low from the cache element of the corresponding processor of the process which initiates the cached data read request; the searched cache elements in which the corresponding cache data is cached are responded, and the corresponding cached data is returned to the corresponding processor process from the searched cache elements. The data processing method can greatly reduce training data acquisition time of computing nodes, and algorithm training time is shortened.

An information processing device includes a first storage unit configured to store a set value indicating a value corresponding to a set item to define a function and flag information indicating whether an initialization of the set value is required, a second storage unit configured to store a flag address identifying a storage location of the flag information in the first storage unit in association with the set item at least, and an initialization unit configured to identify the flag information for each set item by using the flag address corresponding to each set item, and if the identified flag address indicates that the initialization is required, initialize the set value corresponding to the set item.

Embodiments of the inventive concept can include a multi-stage mapping technique for a page cache controller. For example, a gigantic virtual page address space can be mapped to a physical page address efficiently, both in terms of time and space. An internal mapping module can implement a mapping technique for kernel virtual page address caching. In some embodiments, the mapping module can include integrated balanced skip lists and page tables for mapping sparsely populated kernel virtual page address space or spaces to physical block (i.e., page) address space or spaces. The mapping module can automatically and dynamically convert one or more sections from a skip list to a page table, or from a page table to a skip list. Thus, the kernel page cache can be extended to have larger secondary memory using volatile or non-volatile page cache storage media.

The invention provides an internal memory reforming method, an internal memory reforming device, electronic equipment and a readable storage medium. The method comprises the steps of detecting an internal memory distribution situation; judging whether an advance reforming condition is met according to the detected internal memory distribution situation; and reforming the internal memory in advance when the internal memory distribution situation meets the advance reforming condition. Therefore, the internal memory is reformed in advance before the internal memory is fragmentized, so that time-consuming internal memory reforming is avoided, when the internal memory is fragmentized, and thus user experience is enhanced.

The invention relates to a method for enabling an MLC (Multi Level Cell) to have a function of an SLC (Single Level Cell). The method comprises the steps of setting a '0' level and a '1' level on each storage unit; writing data into the MLC by simulating a writing method of the SLC. By adopting the technical scheme, the MLC can be enabled to have the writing performance of the SLC and also have the characteristics of high stability and long service life of the SLC.

The invention provides a single-chip microcomputer burn-writing method, device and system and a single-chip microcomputer. The method comprises the steps of: acquiring a file compiled by an principal computer; according to an address conversion strategy corresponding to a single-chip microcomputer, performing address conversion on a first address involved in the file to obtain a second address of the single-chip microcomputer; according to a data quantity of single burn-writing of the single-chip microcomputer, performing burn-writing on data corresponding to the first address in the file at the position of the second address obtained through conversion of the first address. Compared with the prior art in which a principal computer performs address conversion, the method performs address conversion according to a corresponding address conversion strategy via a single-chip microcomputer, so that a principal computer has greater universality and is applicable to single-chip microcomputers of different chip types. The technical problem of poor universality of a principal computer in the prior art is solved.

The embodiment of the invention discloses a data reading method and device. The method comprises the steps that an initial logical address of target data and the total length of the logical address are calculated; FTL is inquired, and an initial physical address and the total length of continuous physical blocks are obtained; whether the total length of mapped continuous physical blocks is larger than or equal to the total length of the logical address or not is judged; if yes, the initial physical address serves as the starting point, the physical address with the corresponding length is read backwards according to the total length of the logical address, if not, the initial physical address serves as the starting point, IO is split into the corresponding physical block length and residual logical address size according to the recorded physical address total length, the data of physical block length is read, then, the physical address is continuously matched with the IO residual logic address size, the frequency of accessing the FTL can be reduced only when the recorded continuous block address is larger than the unit mapping granularity, the inquiring time is shortened, and the SSD performance is improved.

The invention discloses a data merging method which is used for merging effective data of a logic block in a replication type nonvolatile storage module. The method comprises a plurality of arranging physical blocks which correspond to the logic block in an appointed mode. In addition, the method further comprises an overleaf physical page, wherein the overleaf physical page conducts data reduction operations and data moving operations in a partial synchronization mode so as to arrange the effective data of the logic block from a first data physical block and a temporary storage physical block to an arranging physical block, and the effective data in the logic block from the arranging physical block are programmed to a second data physical block. Moreover, the data merging method further comprises the step of remapping the logic block to the second data physical block. The data merging method is capable of shortening the time of data merging and increasing the reliability of data.