5 results about "Memory management" patented technology

A system and method are provided for in-network power management of network-connected devices. A first computing device, having a power management module, is able to access an in-network computing device table stored in a local memory, of network-connected computing devices cross-referenced to computing device processing capabilities. The power management module retrieves processing capabilities from the in-network computing device table for a network-connected second computing device, and sends a Wake-on-Local Area Network (LAN) message to the second computing device. Subsequently, the power management module sends a server-on-cloud power management message (power management packet) to the second computing device, with instructions for enabling capabilities related to processing or memory management.

The invention discloses a method for distributing hybrid memory, which is characterized by including the following steps: configuring the exclusive memory of a browser and the threshold value used for the memory of the web browser; judging whether the size of the memory applied by the browser exceeds the threshold value used by the browser memory; distributing the memory applied by the browser from the exclusive memory of the non browser in the system; and releasing the memory applied by the browser and enabling other modules to be reused. The invention also discloses a system and a browser for distributing hybrid memory. By utilizing the embodiment and hybrid memory distribution, not only the exclusive memory of the browser can be utilized for effective and economical memory management strategy, but also the memory pressure caused by the exclusive memory of the browser on the system can be avoided to the maximum degree, as a result, the memory waste of the browser caused by producing a large amount of memory fragments can be avoided, and the memory application speed is improved.

Providing memory management unit (MMU)-assisted address sanitizing in processor-based devices is disclosed. In one aspect, a processor-based device provides an MMU that includes a last-level page table that is configured to store page table entry (PTE) tokens for validating memory accesses, as well as fragment order indicators representing a count of page fragments for each memory page in the system memory. Upon receiving a memory access request comprising a pointer token and a virtual address of a memory fragment within a memory page of the system memory, the MMU uses the virtual address and the fragment order indicator of the PTE corresponding to the virtual address to retrieve a PTE token for the virtual address from the last-level page table, and determines whether the PTE token corresponds to the pointer token. If so, the MMU performs the memory access request using the pointer, and otherwise may raise an exception.