64 results about "Parallel computing" patented technology

Some embodiments provide an optimized multi-hit caching technique that minimizes the performance impact associated with caching of long-tail content while retaining much of the efficiency and minimal overhead associated with first hit caching in determining when to cache content. The optimized multi-hit caching utilizes a modified bloom filter implementation that performs flushing and state rolling to delete indices representing stale content from a bit array used to track hit counts without affecting identification of other content that may be represented with indices overlapping with those representing the stale content. Specifically, a copy of the bit array is stored prior to flushing the bit array so as to avoid losing track of previously requested and cached content when flushing the bit arrays and the flushing is performed to remove the bit indices representing stale content from the bit array and to minimize the possibility of a false positive.

A method, apparatus, and computer program product for using a multi-core integrated circuit having cores with differing performance characteristics. The cores are arranged into high and low performance groups and tasks are assigned according to their priority to either a high or low performance group.

Various methods and apparatuses (such as computer readable media implementing the method) are described that relate to proximate placement of sequential cells of an integrated circuit netlist. For example, the preliminary placement is received; and based on the preliminary placement, a group of sequential cells is identified as being subject to improved power and/or timing upon subsequent placement. In another example, identification is received of a group of sequential cells subject to improved power and/or timing upon subsequent placement; and proximate placement is performed of the identified group of sequential cells. In yet another example, a proximate arrangement of a group of sequential cells is received; and if proximate placement fails, then the group of sequential cells is disbanded and placement is performed of the sequential cells of the disbanded group.

A method and system for allowing a processor or I/O master to address more system memory than physically exists are described. A Compressed Memory Management Unit (CMMU) may keep least recently used pages compressed, and most recently and/or frequently used pages uncompressed in physical memory. The CMMU translates system addresses into physical addresses, and may manage the compression and/or decompression of data at the physical addresses as required. The CMMU may provide data to be compressed or decompressed to a compression/decompression engine. In some embodiments, the data to be compressed or decompressed may be provided to a plurality of compression/decompression engines that may be configured to operate in parallel. The CMMU may pass the resulting physical address to the system memory controller to access the physical memory. A CMMU may be integrated in a processor, a system memory controller or elsewhere within the system.

A multiprocessor system includes a main memory and multiple processing cores that are configured to execute software that uses data stored in the main memory. In some embodiments, the multiprocessor system includes a data streaming unit, which is connected between the processing cores and the main memory and is configured to pre-fetch the data from the main memory for use by the multiple processing cores. In some embodiments, the multiprocessor system includes a scratch-pad processing unit, which is connected to the processing cores and is configured to execute, on behalf of the multiple processing cores, a selected part of the software that causes two or more of the processing cores to access concurrently a given item of data.

A system, method and computer program product for optimizing handling of guest code in a Virtual Machine include code for identifying, in the guest code, a predetermined pattern that includes privileged but unsafe instructions and an instruction that raises an exception; code for executing the guest code in a native mode; code for, upon encountering the instruction that raise the exception, transferring control to a Virtual Machine Monitor; code for emulating the pattern in the Virtual Machine Monitor; and code for rolling back the effects of privileged but unsafe instructions and any intervening instructions to ensure correct Virtual Machine Monitor context. The pattern can include, for example, a privileged but unsafe instruction, followed by safe instructions, followed by an exception raising instruction, followed by safe instructions, followed by a privileged but unsafe instruction. Optionally, the most frequently occurring patterns can be placed in a cache, for use by the Virtual Machine Monitor to verify their presence in the guest code.

The invention discloses a control method of a multi-axis motion card control system, and relates to the technical field of mechanical automatic control. The method includes the following steps that a user sends instructions to a DSP in a motion control card through an upper computer; a instruction communication module in the DSP regularly scans an FIFO buffer region and a DPRAM buffer region in an FPGA; when reading the instructions, an instruction analysis module preferentially reads instructions in an emergency instruction circular queue, if emergency instructions need to be executed, the emergency instructions are firstly read, and if no instructions exist in an emergency instruction cache, instructions in an ordinary instruction circular queue are read; after the instructions are taken out from the circular queue, the instructions are analyzed; a speed planning module and an interpolation module calculate speed values of axes according to motion types and parameters. By the adoption of the method, operation efficiency of the system and data processing efficiency are improved, and high efficiency of operation of the system and data continuity are effectively guaranteed.

Branch prediction logic is enhanced to provide a monitoring function for certain conditions which indicate that the use of separate BHTs and predicted target address cache would provide better results for branch prediction. The branch prediction logic responds to the occurrence of the monitored condition by logically splitting the BHTs and count cache so that half of the address space is allocated to a first thread and the second half is allocated to the next thread. Prediction-generated addresses that belong to the first thread are then directed to the half of the array that is allocated to that thread and prediction-generated addresses that belong to the second thread are directed to the next half of the array that is allocated to the second thread. In order to split the array, the highest order bit in the array is utilized to uniquely identify addresses of the first and the second threads.

In general, techniques are described for performing an intra block copying process to code video data. A video decoding device that includes a memory and one or more processors may perform the techniques. The memory may be configured to store a current block of a picture. The processors may be configured to perform an intra block copying process to decode the current block using a prediction block that is from a same slice or a same tile as that in which the coded current block resides, the prediction block restricted to be within a search region that only includes the same slice or the same tile as that in which the coded current block resides.

A system and method to defragment a memory is disclosed. In a particular embodiment, a method includes loading data stored at a first physical memory address of a memory from the memory into a cache line of a data cache. The first physical memory address is mapped to a first virtual memory address. The method further includes initiating modification, at the data cache, of lookup information associated with the first virtual memory address so that the first virtual memory address corresponds to a second physical memory address of the memory. The method also includes modifying, at the data cache, information associated with the cache line to indicate that the cache line corresponds to the second physical memory address instead of the first physical memory address.

The present invention provides a method and system for scheduling a transaction request to a central processing unit in a computing system (11), comprising polling at least one central processing unit to determine the current load on the least one central processing unit (10), allocating the transaction request to one the at least one central processing unit (12), or if the current load is above a predetermined threshold, delaying execution of the transaction request for a predetermined delay time (14).

A microcontroller capable of improving processing performance as a whole by executing different programs by a plurality of CPUs and capable of detecting abnormality for safety-required processing by evaluating results of the same processing executed by the plurality of CPUs. A plurality of processing systems including CPUs and memories are provided, data output from the CPUs in each of the processing systems is separately compressed and stored by compressors for each of the CPUs, respectively. The compressed storage data is mutually compared by a comparator, and abnormality of processing can be detected when the comparison result indicates a mismatch. Even when the timings by which the same processing results are obtained are different when the plurality of CPUs asynchronously execute the same processing, the processing results of both of them can be easily compared with each other since compression is carried out by the compressors. Moreover, since the comparison of the comparator is enabled when comparison enable is given from all the CPUs, the comparison operation result can be obtained based on the timing at which the results of compression by the plurality of compressors are determined.

System and method for testing a DUT that includes a multiprocessor array (MPA) executing application software at operational speed. The application software may be configured for deployment on first hardware resources of the MPA and may be analyzed. Testing code for configuring hardware resources on the MPA to duplicate data generated in the application software for testing purposes may be created. The application software may be deployed on the first hardware resources. Input data may be provided to stimulate the DUT. The testing code may be executed to provide at least a subset of first data to a pin at an edge of the MPA for analyzing the DUT using a hardware resource of the MPA not used in executing the application software. The first data may be generated in response to a send statement executed by the application software based on the input data.

Methods, apparatuses, and computer program products for provisioning aggregate computational workloads and air conditioning unit configurations to optimize utility of air conditioning units and processing resources within a data center are provided. Embodiments include for each air conditioning unit within the data center, determining a thermal zone generated by the air conditioning unit; for a given aggregate computational workload, identifying a plurality of computational workload configurations, each computational workload configuration indicating spatial assignments of the aggregate computational workload among a plurality of processing resources within the data center; for each computational workload configuration, calculating a total minimum energy consumption of the air conditioning units and the processing resources; and selecting the computational workload configuration with the lowest total minimum energy consumption and the determined lowest power air conditioning unit configuration corresponding with the selected computational workload configuration.

The invention discloses a detection method and apparatus for a memory leak bug. The method comprises: obtaining a memory object record currently selected in memory data, wherein the memory data are recorded by a memory of a terminal and generated during use of an application in the terminal, and the memory data comprise one or more memory object records; drawing an object picture indicated by the currently selected memory object record in a predetermined display region; judging whether the object picture is stored in a cache of the terminal or the object picture is displayed by a current interface of the application to obtain a judgment result; and determining whether the application has the memory leak bug or not by using the judgment result. Through embodiments of the invention, the problem of low detection accuracy of detecting a memory leak bug by querying code logic of a picture object in the prior art is solved, so that the effect of accurately detecting the memory leak bug generated by the picture is achieved.

The invention provides a gene data analysis method and a heterogeneous scheduling platform. Assembly line management is performed on tasks to be executed through interaction among a controller, a GPU,an FPGA and a CPU by means of load balancing. The method specifically comprises the following steps: reading and processing a to-be-analyzed gene sequencing file, and storing obtained gene data intoa memory; and reading the gene sequence in the memory and allocating the gene sequence to the processor which is currently in an idle state and/or is not overloaded by combining the load and the running state of the processor by the controller, executing multi-task computational analysis, correcting and converting a computational result, generating an analysis report according to statistics standard output information, and completing data analysis. Load balance is monitored in real time in the analysis process, and if the load for processing the current task is in shortage, computing resourceacceleration processing is improved; correspondingly preposed task computing resources are reduced to reduce input; and the efficiency of analyzing and interpreting the multi-task gene data in unit time is greatly improved.

Device for transferring data between two asynchronous systems communicating via a FIFO memory. The first system comprises a write pointer register and the second system comprises a read pointer register to the FIFO. Each pointer register is associated with a primary shadow register and a secondary shadow register. The primary shadow register is located in the same sub-assembly as the pointer register with which it is associated, and episodically receives a copy of this pointer register. The secondary shadow register is located in the other sub-assembly, and episodically receives a copy of the primary shadow register. Thus, each system has its own pointer register, its associated primary shadow register, and the secondary shadow register associated with the pointer register of the other system.

In a reconfigurable SIMD processor, a unit of operation for executing an instruction corresponds to one group, and the one group that includes a plurality of PEs implements at least a part of an operation unit that executes at least one of an integer divide instruction: a floating decimal point add/subtract instruction; a floating decimal point multiply instruction; and a floating decimal point divide instruction, using operation units and general purpose registers provided in a plurality of the PEs. The number of the PEs that compose the one group is varied in accordance with the instruction.

In one embodiment, a computer system performs a method for reconfiguring the data object layout within a software application binary. The method involves the computer system instantiating a software application binary. The computer system monitors the software application to identify a degree of use of each data object during instantiation of the software application. The computer system stores information that includes the degree of use of data objects monitored. The computer system terminates the software application. The computer system reconfigures the data object layout based on the stored information such that the data objects which satisfied a threshold degree of use are placed in a high-use portion of the application binary, and those data objects which failed to satisfy the threshold degree of use are placed in a low-use portion of the application binary such that order of data objects differs from the first instance of the software application.

The invention relates to a data processing method and device and a related product, the related product comprises a board card, the board card comprises a plurality of artificial intelligence processors, and memories corresponding to the artificial intelligence processors are multi-channel memories; Wherein the target artificial intelligence processor is used for receiving an artificial intelligence processor calculation instruction sent by a universal processor CPU through a target parallel thread and then passing through a memory channel corresponding to the target parallel thread. By adopting the method, smooth operation of the user-defined activation function in the neural network processor can be realized.

The invention relates to a word processing software version compatible method, which comprises reading data content from a word processing file; reading version information stored in the word processing file; loading the date content according to the object information, paragraph information and row information to generate a layout content of the word processing file; and displaying the layout content. The invention effectively assure the layout uniformity of different versions of word processing software opening under different software environments through the layout information stored in the word processing file, so as to realize version compatibility of different versions of word processing software under different software environments, especially to assure character amount uniformity in each row of the file, not causing character flowing in rows.

The invention discloses a multi-machine distributed time sequence task allocation method based on a non-deadlock contract net algorithm, which belongs to the technical field of task allocation. The implementation method comprises the following steps that a time sequence task allocation model isestablished aiming at a time sequence constraint problem of multi-unmanned aerial vehicle cooperative task allocation, and a time sequence task deadlock criterion is proposed; in the task sorting process of a contract net algorithm, the influence of a coupling time sequence task is fully considered, a nearest neighbor task is preferentially selected, a task sorting scheme meeting deadlock constraints is generated in combination with deadlock criterion recursive backtracking used for eliminating an infeasible sorting scheme, a bid invitation unmanned aerial vehicle selection mechanism and algorithm convergence conditions are improved, a non-deadlock contract net (DF-CNP) algorithm based on a competition mechanism is further proposed, the non-deadlock contract net (DF-CNP) algorithm is parallel under a distributed architecture, and a multi-unmanned aerial vehicle non-deadlock time sequence task allocation result is efficiently output. The method is based on a competition mechanism, so that the method has the characteristic of high optimization efficiency.

The embodiment of the invention provides a generation and verification method and device of a verification code picture. The generation method comprises the following steps: selecting a plurality of first elements and a plurality of second elements, wherein there is a preset association relationship between each first element in the plurality of first elements and at least one second element in the plurality of second elements; determining a picture to be synthesized, and determining the positions of each first element and each second element in the picture to be synthesized; and synthesizing the plurality of first elements and the plurality of second elements to the picture to be synthesized according to the positions of each first element and each second element, and obtaining the verification code picture. The generation method of the verification code picture provided by the invention solves the problem that the prior art cannot effectively prevent a machine program from recognizing a verification code.