Device for transferring data via write or read pointers between two asynchronous subsystems having a buffer memory and plurality of shadow registers

[0026]FIG. 5 illustrates a preferred embodiment of the invention. A buffer 390 is arranged to allow transmission between two asynchronous subsystems. Memory 390 is typically a FIFO-type (First In First Out) memory 390 or any operationally equivalent element such as for example a register bank, etc., located on the data path separating two asynchronous subsystems 300 and 350 clock-actuated by two separate clocks clka and clkb. Preferably, FIFO memory will be carried out by means of a dual port memory having a write port and a read port each operating with a separate clock (clka and clkb).

[0027]Moreover, in both subsystems 300 and 350, first and second pointer registers 301 and 351 are found that contain the write pointer and read pointer of the next memory cell, respectively.

[0028]In order to avoid any data transfer error, the device is designed to prevent receive sub-assembly 350 from reading data before transmit sub-assembly 300 (property PR1). Conversely, transmit sub-assembly 300 sh