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104results about "Error prevention" patented technology

Adaptive device-initiated polling

A method includes periodically sending a polling call to an enterprise system outside the firewall at a first polling rate during normal operating conditions, monitoring for a fault condition, periodically sending polling calls to the device outside the firewall at a second polling rate when a fault condition is detected, the second polling rate being higher than the first polling rate. The second polling rate is used as result of a fault condition. The method also includes sending a problem report with the polling calls when the fault condition is detected.
Owner:PARAMETRIC TECH CORP

Delay-reduced stall avoidance mechanism for reordering a transport block

InactiveUS20060062223A1Reduce transmission delayAvoid procrastinationNetwork traffic/resource managementError preventionMissing dataUplink transmission
A method for implementing a stall avoidance mechanism during uplink transmission of data blocks from transmitter to a receiver includes first determining a missing data block in response to a successful receipt of a received data block at the receiver. Once the missing data block is determined, the receiver requests retransmission of the missing data block. The receiver starts a timer when the request for retransmission is made such that the timer has a time value based on the number of reception attempts of the received data block made by the receiver.
Owner:NOKIA SOLUTIONS & NETWORKS OY

Load balancing in a virtual private network

A network system (10). The system comprises a plurality of nodes (PE, CE). Each node in the plurality of nodes is coupled to communicate with at least one other node in the plurality of nodes. Further, each node in the plurality of nodes is coupled to communicate to another node via a respective primary path and via a respective backup path. Still further, each node in the plurality of nodes is operable to perform the steps of, when receiving network traffic as a receiving node, detecting delay (110, 120; 130, 140; 160, 170) in traffic received from a transmitting node, and, in response to detecting delay, communicating a signal to the transmitting node. In response to the signal, the transmitting node is operable to dynamically adjust (150; 190) a distribution of traffic through a respective primary path and a respective backup path from the transmitting node to the receiving node.
Owner:RPX CORP

HIGH SPEED PLC NETWORK-ETHERNET BRIDGE SYSTEM SUPPORTING QoS

Provided is a bridge system of a high-speed PLC network and Ethernet. The bridge system includes a QoS control unit for controlling a QoS process of an entire bridge system; a flow managing unit for storing and managing connection information on a flow, QoS information required by each flow, and information required for executing a bridge function; a bridge QoS processing unit for allocating and managing internal resources of the bridge system and providing the QoS by controlling the QoS control unit and making reference to information stored in the flow managing; a PLC QoS processing unit for managing the QoS of the PLC network by control of the QoS control unit; and an Ethernet QoS processing unit for managing a link state of the Ethernet and providing the link state to the QoS control unit.
Owner:ELECTRONICS & TELECOMM RES INST

Transmitting data in a power line network using link quality assessment

InactiveUS6891796B1Transmission/receiving by adding signal to waveError preventionPower line networkQuality assessment
A method for selecting a communication path between two nodes of a powerline network using a link quality assessment algorithm which selects a communication path based on an analysis of historical data regarding the effective throughput of data transmitted between different nodes of the network. The algorithm is also used to select an appropriate gear for such communication based on an analysis of historical data regarding the unit error rates of data transmitted between the two nodes.
Owner:ENIKIA

Method for transmitting and storing downlink data, base station and terminal

The invention relates to the technical field of communication, and discloses a method for transmitting and storing downlink data, a base station and a terminal. In the scheme, when the base station transmits the downlink data at each time, a bit selection manner adopted by the base station enables that the length and the start point of a sequence expected to receive in initial transmission (or repeat transmission) of the same code block by a terminal in any type are same to the length and the start point of a sequence to be sent by the same code block determined by a sending end, such that the terminal decodes reliably; if decoding is failed, the start point of the sequence in the initial transmission (or repeat transmission) of the same code block stored by the terminal at each time is the same to the start point of the sequence to be sent in the initial transmission (or repeat transmission) of the same code block determined by the sending end; the disadvantage that decoding cannot be carried out accurately due to the fact that storage cannot be carried out accurately when the terminal stores a retransmission code block of the same code block at each time can be avoided; and thus, the decoding accuracy of the terminal is increased.
Owner:HUAWEI TECH CO LTD

Mixed modified weighted bit-flipping LDPC decoding algorithm

ActiveCN103281090AError preventionError correction/detection using multiple parity bitsRound complexityLdpc decoding
The invention discloses a mixed modified weighted bit-flipping LDPC decoding algorithm. The mixed modified weighted bit-flipping LDPC decoding algorithm comprises a first step of initializing a decoder and measuring and calculating parameters, a second step of calculating syndromes of a check matrix, wherein if all syndromes are zero, the decoding is successfully achieved and then the process is finished and if not all syndromes are zero, a third step is carried out, the third step of calculating the judgment standard value En1 of a main algorithm and the judgment standard value En2 of an auxiliary algorithm according to the parameters of the first step and a verifying result of the second step, a fourth step of defining a bit corresponding to the position p as an error bit according to the judgment standard value En1 of the main algorithm and defining a bit corresponding to the position q as an error bit according to the judgment standard value En2 of the auxiliary algorithm, a fifth step of rectifying the bit corresponding to the position p and the bit corresponding to the position q at the same time or only rectifying the bit corresponding to the position p, and a sixth step of repeating the second step to the fifth step, wherein when the decoding is successfully achieved or a maximum number of iterations is reached, the iteration is stopped, and a decoding sequence is output. The mixed modified weighted bit-flipping LDPC decoding algorithm has the advantages that the decoding property is good, computation complexity is low, and hardware is easy to achieve.
Owner:SOUTH CHINA UNIV OF TECH
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