Patents
Literature
Hiro is an intelligent assistant for R&D personnel, combined with Patent DNA, to facilitate innovative research.
Hiro

4 results about "Coincidence" patented technology

A coincidence is a remarkable concurrence of events or circumstances that have no apparent causal connection with one another. The perception of remarkable coincidences may lead to supernatural, occult, or paranormal claims. Or it may lead to belief in fatalism, which is a doctrine that events will happen in the exact manner of a predetermined plan.

Method for planning code word in sector of TD-SCDMA system

InactiveCN1728622AReduce the impact of interferenceImprove anti-interference abilityCode division multiplexRadio transmission for post communicationParallel computingSynchronization code division multiple access
The method includes steps: (1) calculating and storing degree of interference between each scrambling code group in all scrambling code groups and other each scrambling code group; the degree of interference indicates degree of crosscorrelation between two scrambling code groups; (2) finding out assignment of sector scrambling code group with minimal total degree of interference in TD-SCDMA system; (3) based on coincidence relation between scrambling code group and down going pilot frequency code, through assigned scrambling code group for each sector, determining down going pilot frequency code for own sector, and selecting a scrambling code for own sector. Considering disturbed condition caused from relativity between composite codes, the invention raises interference killing feature of system and lowers influence on capacity of TD-SCDMA system from interference between codes in same frequency in network.
Owner:CHINA ACAD OF TELECOMM TECH

Demultiplexer circuit

InactiveUS20050220089A1Improve data transfer rateMultiplex system selection arrangementsParallel/series conversionShift registerSignal on
Demultiplexer capable of coping with bit deviation of a comma code to suppress increase of operating frequency. The demultiplexer comprises a circuit (20) serially supplied with received data to perform serial-to-parallel conversion on the received data, a comma detection circuit (30) for activating a comma detection signal on detection of coincidence between the serial data transferred on parallel paths with clocks corresponding to received clocks halved in frequency and a comma code, and a control circuit (137-139, 40) for elongating and outputting the activated time duration of the comma detection signal by a predetermined time. The demultiplexer also includes a recovery clock generating circuit (50) composed of a state machine transferred between different states based on the frequency-halved clocks and which, on receipt of an output signal of a control circuit (40), varies the period of the recovery clock to output the resulting clock. The demultiplexer also includes first and second delay circuits (131-133, 134-136) and first and second shift registers (121-125, 126-130) for receiving outputs of the first and second delay circuits to convert outputs into parallel data. The demultiplexer also includes a latch circuit (70) receiving outputs of respective stages of the first and second shift registers in parallel and sampling parallel outputs with recovery clocks to output resulting parallel data. In case of occurrence of bit deviation, recovery clocks are elongated by a predetermined time duration for only one period depending on the state of bit deviation.
Owner:RENESAS ELECTRONICS CORP
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Try Eureka
PatSnap group products