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69 results about "Theoretical computer science" patented technology

Theoretical computer science (TCS) is a subset of general computer science and mathematics that focuses on more mathematical topics of computing and includes the theory of computation. It is difficult to circumscribe the theoretical areas precisely.

Efficient Pipelined Binary Search

An apparatus and machine readable storage medium for performing a binary search of an ordered list containing 2N values, where N is an integer greater than one. The apparatus may include a pipeline having N stages numbered 1 to N in sequence. Stage M of the pipeline, where M is in integer from 1 to N, may include a memory storing 2M-1 values from the ordered list, a comparator to compare the key to a value read from the memory based on comparison results from previous stages in the pipeline, and a result storage register to store a comparison result from the comparator and the comparison results from the previous stages in the pipeline.
Owner:IXIA

Malicious software API call sequence detection method based on graph convolution

ActiveCN111259388AImprove bindingFlexible organizational structurePlatform integrity maintainanceNeural architecturesCall graphAlgorithm
The invention provides a malicious software API (Application Program Interface) call sequence detection method based on graph convolution. The method comprises the following steps: acquiring and recording API call sequence information of processes and sub-processes when a large number of software samples run; performing vectorization processing on the API calling sequence information; extracting aparameter relationship, a dependency relationship and a sequence relationship of the API function; establishing an API call graph; inputting the API call graph into a graph convolutional neural network for training to obtain a malicious software detection network model; collecting API calling sequence information of processes and sub-processes when the executable file to be detected runs; constructing an API call graph of the executable file to be detected, then inputting the API call graph of the executable file to be detected into the malicious software detection network model, If the output result of the malicious software detection network model is 1, indicating that the judgment result is malicious software; If the output result of the malicious software detection network model is 0,indicating that the judgment result is normal software.
Owner:SUN YAT SEN UNIV

Compile time linking via hashing technique

InactiveUS20060130020A1Simple processRapid techniqueLink editingProgram controlAddress resolutionMachine code
A linker is usually used, in post processing of compiling high-level languages such as C into machine executable language, to bind separately compiled object files and resolve the addresses (142) of global variables (140) declared in the separate files. The invention proposes linking during compile time by using a special purpose hash table called global variables hash table (130) shared among the separate files. This results in a collection of processed object files that are coherent in terms of their addresses (142) for global variables (140) that could be further assembled correctly into machine executable code. This method is useful for compiling separate high level language source files to generate executable machine code employing a technique of address resolution across separate modules.
Owner:AXIOMATIC SOLUTIONS

Radiation tolerant combinational logic cell

InactiveUS20070109865A1Increase energy levelReduce sensitivityRead-only memoriesDigital storageCMOSData set
A system has a reduced sensitivity to Single Event Upset and/or Single Event Transient(s) compared to traditional logic devices. In a particular embodiment, the system includes an input, a logic block, a bias stage, a state machine, and an output. The logic block is coupled to the input. The logic block is for implementing a logic function, receiving a data set via the input, and generating a result f by applying the data set to the logic function. The bias stage is coupled to the logic block. The bias stage is for receiving the result from the logic block and presenting it to the state machine. The state machine is coupled to the bias stage. The state machine is for receiving, via the bias stage, the result generated by the logic block. The state machine is configured to retain a state value for the system. The state value is typically based on the result generated by the logic block. The output is coupled to the state machine. The output is for providing the value stored by the state machine. Some embodiments of the invention produce dual rail outputs Q and Q′. The logic block typically contains combinational logic and is similar, in size and transistor configuration, to a conventional CMOS combinational logic design. However, only a very small portion of the circuits of these embodiments, is sensitive to Single Event Upset and/or Single Event Transients.
Owner:IDAHO UNIV OF +1

System and method for executing hybridized code on a dynamically configurable hardware environment

InactiveUS7032103B2Software engineeringGeneral purpose stored program computerMultiple contextTheoretical computer science
A system and method for executing previously created run time executables in a configurable processing element array is disclosed. In one embodiment, this system and method begins by identifying at least one subset of program code. The method may then generate at least one set of configuration memory contexts that replaces each of the at least one subsets of program code, the at least one set of configuration memory contexts emulating the at least one subset of program code. The method may then manipulate the at least one set of multiple context processing elements using the at least one set of configuration memory contexts. The method may then execute the plurality of threads of program code using the at least one set of multiple context processing elements.
Owner:QUALCOMM INC

Data formats and usage for massive point-to-point route calculation

The invention is directed to a method by which optimal paths are found between one or more start destinations and one or more end destinations. First destination and travel data is converted into a node and edge data format, wherein the nodes represent start points and the the edges have a weight related to a travel weight. These nodes and edges are subdivided into subsets. The paths between the start nodes and each of the end nodes are determined using the node and edge representations stored in the subsets. A selected union of subsets is determined that contains the start end end destinations. The optimal paths are determined by using the travel values associated with the edges connecting the nodes. The union of subsets, which may comprise less than the full amount of subsets, is loaded for the path determination. Or, when the path determination perceives that a relevant boundary has been reached in a path determination, that next subset in the union of subsets is loaded. The newly loaded subset is “joined” to the already loaded subsets, thus allowing the completion of the path determination.
Owner:GEOTAB

Method and device for data detection in communication system and computer storage medium

ActiveCN110830395AChannel estimationTime domainInterference (communication)
The embodiment of the invention provides a method and device for data detection in a communication system and a computer readable medium. The method described herein includes receiving, at a receivingdevice, a set of reference signal time domain symbols from a target transmitting device, the reference signal having a comb distribution with a spacing factor of N in the frequency domain, N being apositive integer not less than 2; for each reference signal time domain symbol in the set, dividing the reference signal time domain symbol into N parts with repeatability; obtaining channel estimation and estimation of a covariance matrix of interference and noise based on N parts of each reference signal time domain symbol in the set; applying an adjustment factor to the estimate of the covariance matrix to obtain a corrected covariance matrix, the adjustment factor being associated with a spacing factor N; and performing data detection based on the channel estimation and the corrected covariance matrix. By utilizing the embodiment of the invention, the performance of data detection can be improved.
Owner:ALCATEL LUCENT SHANGHAI BELL CO LTD +1

Program execution device and electronic apparatus

InactiveUS20080189507A1Short processing timeShort timeRuntime instruction translationMemory adressing/allocation/relocationTheoretical computer scienceLookup table
A program execution device includes: a lookup table storage section that stores a lookup table stipulating a plurality of relations between a plurality of input data and a plurality of output data that are results of operation conducted on the plurality of input data; a program storage section that stores a program including a command directing to obtain one of the output data that is a result of the operation conducted on one of the input data, which is defined by the one of the input data and the operation; and a program execution section having a first cycle of designating the one of the input data in the command to the lookup table in the lookup table storage section, and a second cycle of receiving the one of the output data corresponding to the one of the input data from the lookup table.
Owner:SEIKO EPSON CORP

Median filtering implementation method for integrated circuit design

InactiveCN104811161AIncrease the median filter rateDigital technique networkTheoretical computer scienceIntegrated circuit
The invention discloses a median filtering implementation method for integrated circuit design. The median filtering implementation method for the integrated circuit design is implemented based on a memory and an FSM. The median filtering implementation method for the integrated circuit design comprises the step S1 of initialization and the step S2 of filtering output. The step S1 of initialization comprises the step that N data which are sorted by size are stored in the memory according to a data structure so as to establish a data table, wherein when the number of stored data is smaller than N, and new data come, polling is conducted from any one end of a stored sorted data table, the stored data and the new data are compared, the appropriate positions of the new data in the sorted data table are found out, the new data are inserted into the sorted data table, and the new data are inserted one by one until the number of the data is equal to N, and therefore initialization is completed. The step S2 of filtering output comprises the steps that the data table is reestablished in a deletion and insertion mode according to the time sequence on the basis of the established data table, and a median of the N data is outputted according to the reestablished data table. When the median filtering implementation method is applied, the hardware cost can be reduced, the median filtering rate can be increased to 700 KHz, the median filtering depth can be increased to 32, and therefore the comprehensive constraint conditions can be changed.
Owner:SHANGHAI PANCHIP MICROELECTRONICS CO LTD

Distributed computing unloading method and device based on deep reinforcement learning

PendingCN114449584AFast convergenceReduce complexityMathematical modelsResource allocationInterference ratioTheoretical computer science
The invention relates to a distributed computing unloading method and device based on deep reinforcement learning. The method comprises the steps that a calculation unloading framework is set, a communication model and a calculation model are established according to the calculation unloading framework, the communication model is used for calculating the signal-to-noise-interference ratio of terminal equipment, the calculation model is used for conducting local calculation and edge calculation on the terminal equipment, and the terminal equipment is calculated based on the calculation unloading framework, the communication model and the calculation model. And modeling a calculation unloading problem into a Markov decision process, and carrying out optimization iteration solution on the Markov decision process by utilizing a depth deterministic strategy gradient algorithm of the double-Critic network to obtain an unloading decision. Due to the fact that the depth deterministic strategy gradient algorithm of the double Critic networks is used for conducting optimization iteration solution, the double Critic networks are respectively fitted, the complexity of fitting of a single Critic network is reduced, the convergence speed of the Critic networks is improved, and the overall convergence speed of the model is greatly improved.
Owner:HUNAN UNIV
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