29 results about "Comparator" patented technology

A phase shift and duty cycle correction circuit is disclosed herein as comprising a programmable digital to analog converter (DAC), a storage device (e.g., a capacitor), a charge sub-circuit and dump sub-circuit for charging and discharging the storage device, respectively, a comparator, and a clock driver circuit. A linearly increasing (or ramped) voltage waveform is generated within the storage device by the charging and discharging actions of the charge and dump sub-circuits; a periodic process which is controlled by opposite phases of the input clock. By programming the DAC control input to change the slicing threshold of the ramped waveform, the circuit and method described herein provides a means for programmable phase shifting and duty cycle correction.

The invention discloses a PWM/PDM double-mode modulation selecting circuit and a double-mode modulation method, which mainly solves the problem that the prior DC/DC converter is not high in average conversion efficiency within a heavy-load range. The whole circuit comprises a bias circuit, a band gap reference voltage source, an error amplifier, an isolation common-source follower, an oscillator, an integrator, a mode judgment comparator, a control comparator, a latch and a driving buffer, wherein the mode judgment comparator and the latch are connected between the output end of the error amplifier and the control end of the oscillator; the magnitude comparison of load current is converted into voltage comparison through the relation of duty cycle and triangular wave; and when the load current is larger, the circuit selects a PWM modulation mode otherwise the circuit selects a PDM modulation mode when the load current is smaller. Under the condition of guaranteeing the performance of the DC/DC converter, the invention improves the average conversion efficiency in a load change interval, and is applicable to the DC/DC switch converter with great load current change, low requirement on circuit volume and high requirement on conversion efficiency.

The invention discloses an analog circuit for detecting the wire breaking of a displacement sensor LVDT, which comprises a displacement sensor LVDT, wherein a primary coil of the displacement sensor LVDT is connected with an excitation signal source. The analog circuit for detecting the wire breaking of the displacement sensor LVDT is characterized in that the output ends of the secondary coils of the displacement sensor LVDT are respectively connected with a test signal and are respectively connected with a multi-channel selection switch through a filter and rectifier circuit, and predetermined different groups and combinations of wire breaking voltages which are output when an LVDT is disconnected are simultaneously connected with the multi-channel selection switch; the two output end voltages of the secondary coils of the LVDT are respectively combined with a group of comparison voltages to be connected with each comparator, and each comparator is connected with the output control end of the multi-channel selection switch through an arithmetic logic OR unit, and the multi-channel selection switch is simultaneously connected with a servo amplifier. The invention can directly achieve the detection of wire breaking state only by a hardware circuit, and the method is simple and reliable.

A microcontroller capable of improving processing performance as a whole by executing different programs by a plurality of CPUs and capable of detecting abnormality for safety-required processing by evaluating results of the same processing executed by the plurality of CPUs. A plurality of processing systems including CPUs and memories are provided, data output from the CPUs in each of the processing systems is separately compressed and stored by compressors for each of the CPUs, respectively. The compressed storage data is mutually compared by a comparator, and abnormality of processing can be detected when the comparison result indicates a mismatch. Even when the timings by which the same processing results are obtained are different when the plurality of CPUs asynchronously execute the same processing, the processing results of both of them can be easily compared with each other since compression is carried out by the compressors. Moreover, since the comparison of the comparator is enabled when comparison enable is given from all the CPUs, the comparison operation result can be obtained based on the timing at which the results of compression by the plurality of compressors are determined.

The present invention discloses a host receiver synchronizer for passive optical networks, and in particular a burst clock data recovery circuit in a host receiver in a bursty asynchronous communication system having a non-data preamble of less than 250 ns, for recovering a clock signal from a subscriber data burst. The circuit comprises: an adjustable oscillator for generating an output clock signal in response to a signal at an input thereof; a first comparator for comparing a frequency and phase of the output clock signal to that of a reference signal and feeding back a first feedback signal to the oscillator input; and a second comparator for comparing the frequency and phase of the output clock signal to that of the data burst and feeding back a second feedback signal to the oscillator input once the output clock signal is locked in frequency with the reference signal. The output clock signal is locked in frequency and phase to the data burst before receipt of the last bit of the preamble. The present invention is advantageous in that the receiver circuit improves synchronized jitter performance over the prior art solutions so that additional timing margin is provided, thereby allowing longer fiber lengths to be supported.

The invention relates to a high-speed serial port load automatic calibration circuit. One end of a port load resistor array of the high-speed serial port load automatic calibration circuit is connected with an analog power supply, the other end is connected with an input end of a first current source, and an output end of the first current source is connected to the ground; one end of a high-precision resistor is connected with an analog power supply, the other end is connected with an input end of a second current source, and an output end of the second current source is connected to the ground; one end of a high-speed serial port resistor array is connected with an analog power supply; a negative input end of a comparator is connected between the port load resistor array and the first current source, a positive input end is connected between the high-precision resistor and the second current source, the comparator compares voltage values of the high-precision resistor and the port load resistor array and outputs a comparison result signal to a digital state machine, the digital state machine generates a control signal to control resistance of the port load resistor array and the high-speed serial port resistor array. The high-speed serial port load automatic calibration circuit provided by the invention realizes automatic calibration of the high-speed serial port load resistor, and achieves an impedance matching effect of a high-speed serial port.

The invention relates to the technology of a power source and an integrated circuit, in particular to a DC-DC converter with the output voltages capable of being adjusted quickly. The DC-DC converter comprises a driving circuit, a PMOS tube MP, an NMOS tube MN, a PWM comparator, an EA amplifier, an inductor L, a capacitor C, a resistor R and a power source Vin. The DC-DC converter is characterized in that a calculating amplifier is further included, the driving circuit, the PMOS tube MP, the NMOS tube MN, the PWM comparator, the EA amplifier, the inductor L, the capacitor C, the resistor R and the power source Vin form a traditional DC-DC converter, and the positive input end and the output end of the calculating amplifier are connected to be used as one end, connected to the capacitor C, of a bumper. The DC-DC converter has the advantages of being simple in structure, easy to achieve, low in power consumption, and capable of achieving quick adjusting of the output voltages of the DC-DC converter only by small domain area. The DC-DC converter is particularly suitable for DC-DC converters.

A comparator is provided and the comparator includes a comparing input unit and a latching unit. Wherein, the comparing input unit has a first input receiving a first comparing signal and has a second input receiving a second comparing signal. The comparing input unit drives a first intermediate node signal at a first intermediate node depending on the first comparing signal according to a first strobe signal, and the comparing input unit drives a second intermediate node signal at a second intermediate node depending on the second comparing signal according to the first strobe signal. The latching unit determines a comparing result according to at least one of the first intermediate node signal and the second intermediate node signal. In addition, the latching unit latches the comparing result according to a second strobe signal.

The invention relates to a lagging comparer, wherein it comprises current source I1, two input MOS tubes, three load MOS tubes, and lagging adjuster for adjusting the threshold value of comparer. When the input MOS tube is NMOS tube, the load MOS tube uses PMOS tube; the single threshold value of circuit is irrelative to the circuit element parameters, that one fixed input voltage of comparer can fix single threshold value; the inventive circuit has asymmetry positive feedback circuit to form the lagging circuit of lagging comparer, to generate threshold voltage and complete comparison. The invention also has positive feedback branch and output branch, MOS tube with static protection and resistance.

The invention relates to a control system, in particular to a building water overflow automatic alarm control system, which aims to solve the problem that a scattered control manner adopted for preventing water overflow of buildings is not suitable for the existing buildings, and centralized control is needed. When tap water or water in a heater accidentally overflows, and overflow sensors are submerged, detection signals are provided for a building water overflow automatic alarm controller by the overflow sensors, the building water overflow automatic alarm controller carries out detection judgment on the signals of the overflow sensors, when the signals meet the action condition of the building overflow automatic alarm controller, a relay control circuit is controlled to act, an alarm circuit is enabled to send out an alarm signal, and an electromagnet valve or an electrically operated valve is driven to act to close an overflow water source. The building water overflow automatic alarm controller comprises one or more hysteresis voltage comparison circuits, and the hysteresis voltage comparison circuits take LM339 voltage comparator integrated circuits as core elements for forming comparison circuits with a hysteresis starting function and a hysteresis closing function. The building water overflow automatic alarm control system is used for monitoring water overflow in the buildings.

The invention discloses a rectifier circuit for piezoelectric energy collectors to solve the problem that the energy consumption of an existing circuit is high and the efficiency of a piezoelectric energy collector is low when the rectifier voltage of the piezoelectric energy collector is greater than 2.5 V. The rectifier circuit comprises a full-wave rectifier bridge (2) and an active diode circuit (4), and further comprises a bias circuit (3). The output end of the full-wave rectifier bridge (2) is connected with the input ends of the active diode circuit (4) and the bias circuit (3). The output end of the bias circuit (3) is connected with the bias voltage end of a comparator in the active diode circuit (4). The output end of the active diode circuit (4) is connected with an energy storage capacitor C3. The rectifier circuit for piezoelectric energy collectors has the advantages of being low in power consumption, high in energy conversion efficiency, and capable of ensuring the energy demand of wireless sensor network node load.

The invention relates to a circuit for realizing constant current control in a primary control switch power converter. The circuit comprises a controller, wherein the controller comprises a sampling/holding circuit, a voltage/current conversion circuit, an oscillator circuit, a flip-flop and a current limiting comparator; the sampling/holding circuit samples and holds feedback voltage VFB and inputs the feedback voltage VFB to the voltage/current conversion circuit; the voltage/current conversion circuit converts the feedback voltage VFB to obtain required control current; the oscillator circuit outputs a corresponding oscillation frequency signal according to the control current, and inputs the oscillation frequency signal to a setting end of the flip-flop; when the oscillation frequency signal is at a high level, an output ends of the flip-flop outputs a high level signal to switch on a driving power tube; and when sampling voltage VCS is higher than reference voltage VREF of an antiphase end of the current limiting comparator, the current limiting comparator outputs a current limiting signal to allow the flip-flop to output a low level so as to switch off the power tube. The circuit is compact in structure, wide in application scope, safe and reliable, and can realize the constant current control.

The invention particularly relates to a memristor-based automatic gain control circuit. The technical scheme is as follows: the circuit consists of a variable gain amplification module (1), a comparator (4) and a peak value detection module (5); the variable gain amplification module (1) consists of an operational amplifier circuit (2) and a memristor (3); a terminal M2 of the memristor (3) is connected with an input end Rc of the operational amplifier circuit (2); an input end Vi of the operational amplifier circuit (2) is externally connected with an input signal Vin; an output end VVGA of the operational amplifier circuit (2) is respectively connected with an input end VVGAP of the peak value detection module (5) and the input end Vw of a peripheral circuit; a terminal M1 of the memristor (3) is connected with an output end Vc of the comparator (4); an input end ViVGAP of the comparator (4) is connected with an output end ViVGA of the peak value detection module (5); and an input end VREF1 of the comparator (4) is externally connected with a reference electric level VREF. The memristor based automatic gain control circuit provided by the invention has the advantages of simple structure, low cost and high accuracy.

The invention provides an explodent elimination circuit. The explodent elimination circuit is used for explodent elimination during power on and power off of an output node of an audio digital-to-analog converter, and comprises four resistors, three positive channel metal oxide semiconductor (PMOS) transistors, two negative channel metal oxide semiconductor (NMOS) transistors, a comparator, a pull-up current source, a pull-down current source and a control logic module, wherein the pull-up current source and the pull-down current source slowly charge the output node or provide a discharge path and can effectively eliminate the explodent of the output node during power on and power off; and the adjustable voltage rise speed and voltage drop speed of the output node are ensured by a current source structure and feedback control. The invention has the characteristics that: the explodent elimination circuit can be widely applied to a power amplifier at the rear end of a single-bit audio digital-to-analog converter, a multi-bit audio digital-to-analog converter or the audio digital-to-analog converter, and can effectively eliminate the explodent caused by abrupt power on or power off of the output node of the audio digital-to-analog converter; the voltage rise time and the voltage drop time of the output node are controllable, complicated control logics are unnecessary, and the power consumption is low.

The invention discloses an adaptive threshold adjusting method for a non-contact intelligent card demodulation system. An additionally-arranged adaptive threshold adjusting circuit in a non-contact IC card is utilized for accomplishment. The adaptive threshold adjusting circuit determines whether a threshold is appropriate according to the number of zeros in a zero number counter. After stabilization of a power-on simulation front end circuit, adjustment is carried out from a greatest threshold downwards, the great number of the zeros means that the threshold is too great, burr generation occurs, a fixed threshold step length is subtracted from a present threshold, after accomplishment of threshold switching of the simulation circuit, next determination is carried out continuously, till the number of the zeros reaches a prescribed range, the threshold reaches an optimum one, or demodulation for a smallest threshold is carried out. According to the adaptive threshold adjusting method, in a field intensity range of 1.5A/m-7.5A/m, for multiple antenna waveforms prescribed in an ISO/IEC14443TypeA protocol, a comparator threshold can be automatically selected, and demodulation data with pause width close to 3mus is outputted.

Each time a sync controller sequentially issues a read request to a memory controller, a count value of a first counter is incremented. When a read operation is conducted for the read request, a count value of a second counter is incremented and the data is transferred to a standby computer. If a memory write instruction is issued during a memory copy operation, an address comparator compares a write address of the memory write instruction with the count values of the first and second counters. If the write address is more than the count values, the memory write operation is permitted. If the write address is equal to the count value of the first counter, the process waits for termination of the data read operation. Otherwise, the write operation is immediately permitted and the write data is transferred to the sync controller. Data of a memory on the active side can be hence copied onto the standby computer without stopping the system operation.

The invention discloses a detection circuit capable of detecting a plurality of arbitrary-combination keys by low cost, and a processing method. The detection circuit comprises control chips and a matrix key circuit, wherein the control chips include a single chip microcomputer, an MCU (Microprogrammed Control Unit), a CPLD (Complex Programmable Logic Device), an FPGA (Field Programmable Gate Array), an ARM (Advanced RISC Machine) and the like; each control chip is provided with R+C pieces of IO (Input/Output) pins; an R wire controls the IO as input and has an external interruption function;in addition, each IO pin has IO function settings, including floating, open-drain, push-pull, upward pull, downward pull and the like; and an AD (Analogue/ Digital) sampling functional or operationalamplifier, a comparator or a plug-in operational amplifier and a comparator are built in the controller chip. The detection circuit has the beneficial effects that no diodes are required, or only a small quantity of diodes is required to realize low-cost any-key no conflict and full-key no conflict, an audion MOS (Metal Oxide Semiconductor) tube and the like can be cooperated to realize IO reuse for LED (Light Emitting Diode) light control.

Tennis players need multiple playing racquets available for their use, and the mass proportions of each one, needs to match all the others exactly, otherwise players will likely experience degradation in their swing mechanics when unmatched racquet's were used.

BOC provides a simplified solution, through comparator testing, which provides a means for mass proportions matching, of 2 tennis racquets or similar swing-able massive implements.

Whereby, a Reference massive object/racquet having a perfected swing mass is directly compared to a 2^nd massive object/racquet having an imperfect swing mass, that can then be adjusted to match the reference objects perfected swing mass, by placing small metal strips of mass by trial [per our plan] onto the frame/moment of 2^nd object. Then finally both tested racquets will become exactly the same perfected swing mass proportions.

An integrated circuit (10), preferably a field programmable gate array—FPGA or an application specific integrated circuit—ASIC—, comprises a level comparator (30) for comparing a level of a comparator input signal and correspondingly providing a comparator output signal (COS). A sampling unit (40) is coupled to the level comparator (30) for sampling (SAM) the comparator output signal (COS). A bit error test unit (60) receives the sampled comparator output signal (SAM) and determine therefrom an indication of a bit error in a sequence of the sampled comparator output signal (SAM).

The invention provides a stable oscillation clock generated inside a chip, at least comprising an oscillation clock generator (OSC generator), a programming controller for controlling clocks with different frequencies and a timing counter, wherein a control signal output by the programming controller for controlling the clocks with the different frequencies is directly connected to the oscillation clock generator (OSC generator); an oscillation clock signal is generated by the oscillation clock generator; the oscillation clock signal is output to outside to be used by different parts of the chip; the oscillation clock signal is connected to the clock input end of the timing counter to adjust the counted quantity of the timing counter; and the counted quantity of the timing counter is connected to a comparator to be compared with a standard performance to generate a feedback signal to a logic control unit of the stable oscillation clock, so as to automatically determine the frequency of the oscillation clock. A designing method of the stable oscillation clock generated inside the chip enables the work of the chip to be more stable and reduces the error rate and the like; and the stable oscillation clock is compact in structure and is safe and reliable.

The invention discloses an MRAM (Magnetic Random Access Memory) sense amplifier capable of offsetting deviation. The MRAM read-out circuit is used as a post-amplifier of the MRAM read-out circuit, andcomprises NMOS tubes M0 and M1 with the same parameters, NMOS tubes M2 and M3 with the same parameters, PMOS tubes M4 and M5 with the same parameters, capacitors C0 and C1, and three same switches K1and K2; the drain electrode of the M2 is connected with the drain electrode of the M4, wherein the connection point is a point A; the grid of M2 is connected with the grid of M4, wherein the connection point is a point B; the drain of M3 is connected with the drain of M5, wherein the connection point is a point C; the grid of M3 is connected with the grid of M5, wherein the connection point is apoint D; the capacitor C0 is connected between the point B and the point C, and the capacitor C1 is connected between the point A and the point D. In the working stage, the capacitor C0 and the capacitor C1 counteract asymmetry of the read-out differential amplifier. A pair of capacitors is added on the basis of a common differential comparator, asymmetry of the differential amplifier can be counteracted, and meanwhile the area of the amplifier does not need to be large.