A
semiconductor chip includes a first
mask logic. The first
mask logic includes a first
mask and a second mask that mask a respective first scan channel output and a second scan channel output. The first mask logic includes at least three enable pins that receive respective enable signals. The three enable signals produce a channel mask enable
encode. The first mask logic includes a first memory that stores a first channel mask enable decode for the first mask and a second memory that stores a second channel mask enable decode for the second mask. The first mask logic includes a first
comparator and a second
comparator. The first and second
comparator compare the respective channel mask enable
decodes to the channel mask enable
encode. The comparators
signal respective masks to mask the respective scan channel when the respective channel mask enable decode matches the channel mask enable
encode.