Programmable phase shift and duty cycle correction circuit and method

a phase shift and duty cycle correction technology, applied in the field of electronic circuits, can solve problems such as significant impact on system performance and/or reliability, one or more system components, and design and operation problems of electronic systems

Active Publication Date: 2006-11-21
CYPRESS SEMICON CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

This patent describes various technical features related to improving the performance of electronic circuits. It explains how these improvements can be achieved through controlling the timing and amplitude differences between two input signals. By adjusting certain parameters, the circuit can achieve better results without sacrificing any functionality. Additionally, it mentions that this technology allows for independent adjustment of specific functions based on their respective requirements. Overall, the patented technology provides improved efficiency and flexibility in electronic circuits.

Problems solved by technology

This patent describes a problem where there is a significant difference in timing between clock cycles caused by factors like temperature fluctuation and power supply changes. These differences lead to errors in determining the best timing for the clock signal. Additionally, the use of phase lock loops (PCB's) introduces delays due to their inherent properties. Consequently, the accuracy of the clock signal degrades over time.

Method used

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  • Programmable phase shift and duty cycle correction circuit and method
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  • Programmable phase shift and duty cycle correction circuit and method

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Embodiment Construction

[0033]An embodiment of an improved phase shift and duty cycle correction circuit is shown in FIG. 2. In general, the improved circuit enables both rising and falling edges of a generated clock signal to be shifted in time by an independently programmable amount. In some embodiments, the programmable amounts may be set by a manufacturer or end-user of the circuit; however, additional circuit components may be provided, in other cases, for detecting and automatically setting an appropriate phase shift amount. By shifting the rising and falling edges of the clock signal, the improved circuit provides a unique means for correcting, or otherwise modifying, a duty cycle of the generated clock signal. In one embodiment, means for adjusting the phase and duty cycle of the generated clock signal may be implemented with a simple digital-to-analog converter (DAC), programmable by a variety of methods, including but not limited to, register bits, hardwired bits, externally supplied inputs, program

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Abstract

A phase shift and duty cycle correction circuit is disclosed herein as comprising a programmable digital to analog converter (DAC), a storage device (e.g., a capacitor), a charge sub-circuit and dump sub-circuit for charging and discharging the storage device, respectively, a comparator, and a clock driver circuit. A linearly increasing (or ramped) voltage waveform is generated within the storage device by the charging and discharging actions of the charge and dump sub-circuits; a periodic process which is controlled by opposite phases of the input clock. By programming the DAC control input to change the slicing threshold of the ramped waveform, the circuit and method described herein provides a means for programmable phase shifting and duty cycle correction.

Description

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Claims

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Application Information

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Owner CYPRESS SEMICON CORP
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