237 results about "Capacitance" patented technology

The present invention discloses a display panel and a display device. A display area is divided into a first display area and a second display area, when the number of pixels of one row of pixels in the second display area is smaller than the number of pixels of one row of the pixels in the first display area, the load of a scanning signal line connected with the row of the pixels in the second display area is smaller than the load of a scanning signal line connected with the row of the pixels in the first display area, and through adoption of a mode of connecting at least one of each scanning signal line connected with each row of the pixels in the second display area with a compensation capacitor, the load of the scanning signal lines connected with the compensation capacitor can be increased, and the load difference from the scanning signal lines in the first display area can be reduced so as to improve the problems that the loads of the scanning signal lines are different to cause uneven data writing-in and uneven display.

A semiconductor device includes a semiconductor substrate including a main surface; a plurality of first interconnections formed in a capacitance forming region defined on the main surface and extending in a predetermined direction; a plurality of second interconnections each adjacent to the first interconnection located at an edge of the capacitance forming region, extending in the predetermined direction, and having a fixed potential; and an insulating layer formed on the main surface and filling in between each of the first interconnections and between the first interconnection and the second interconnection adjacent to each other. The first interconnections and the second interconnections are located at substantially equal intervals in a plane parallel to the main surface, and located to align in a direction substantially perpendicular to the predetermined direction.

The invention provides a control method of a flyback converter. The control method is a control method in a mixed control mode; in other words, the flyback converter works in a non-complementation state under light loads, the clamp switch pipe on time is shortened through down conversion, and light load losses are effectively reduced through down conversion; flyback converter works in a fixed-frequency drive complementation state under heavy loads, and the clamp switch pipe on time is prolonged. Compared with the prior art, the control method has the advantages that the voltage stress of a main switch pipe and a clamp capacitor can be effectively reduced, the main switch pipe off losses can be reduced, the clamp circuit current change slope is decreased, the EMI interference is reduced, the secondary current change slope is decreased, and the longer detection reaction time is provided for synchronous rectification. Meanwhile, the working area of a magnetic core in the third quadrant is enlarged, the maximum flux density is reduced, and the size of the magnetic core is reduced.

The invention provides a wireless charging sending device, a wireless charging system and a charging control method thereof. The sending device comprises an emission coil used for emitting electricity energy of the sending device, an oscillating and frequency-modulating module used for enabling the emission coil to generate LC resonance and modulating the capacitance in the LC resonance so as to change the resonance frequency of the LC resonance, an emission end sampling module used for collecting voltage and currents of the sending device, a first control module used for controlling the resonance frequency of the LC resonance in the oscillating and frequency-modulating module and controlling the charging energy sending process according to the collected voltage and the collected currents of the sending device, the voltage of a receiving device and resonance frequency corresponding to the highest charging efficiency, a first communication module used for wireless communication between the sending device and the receiving device, and a power supply module. The sending device, the charging system and the charging control method can realize the adjustment of the resonance frequency of the LC resonance so as to have the advantage of improving the charging efficiency of the charging system.

In a first structure, a metal gate portion may be laterally recessed from a substantially vertical surface of a gate conductor thereabove. A cavity is formed between the metal gate portion and a gate spacer. In a second structure, a disposable gate portion is removed after laterally recessing a metal gate portion therebeneath and forming a dielectric layer having a surface coplanar with a top surface of the disposable gate portion. (We have to include the inner spacer without a metal recess). An inner gate spacer is formed over a periphery of the metal gate portion provide a reduced overlap capacitance. In a third structure, a thin dielectric layer is employed to form a cavity next to the metal gate portion in conjunction with the inner gate spacer to provide reduced overlap capacitance.

A quad photoreceiver includes a low capacitance quad InGaAs p-i-n photodiode structure formed on an InP (100) substrate. The photodiode includes a substrate providing a buffer layer having a metal contact on its bottom portion serving as a common cathode for receiving a bias voltage, and successive layers deposited on its top portion, the first layer being drift layer, the second being an absorption layer, the third being a cap layer divided into four quarter pie shaped sections spaced apart, with metal contacts being deposited on outermost top portions of each section to provide output terminals, the top portions being active regions for detecting light. Four transimpedance amplifiers have input terminals electrically connected to individual output terminals of each p-i-n photodiode.

A transconductance amplifier mirror circuit is connected to an electrode for sensing the capacitance of the electrode with reference to ground, or the capacitance between the electrode and another electrode. A voltage level change is produced on the electrode connected to the transconductance amplifier mirror circuit to cause the transconductance amplifier mirror circuit to supply charges to or drain charges from a charge calculation circuit. The charge amount variation is converted to a signal for calculating the sensed capacitance.

In one aspect of the invention, an acoustic device has a first coupled resonator filter (CRF) and a second CRF electrically coupled to one another in series. Each CRF has an input port, an output port, a bottom film bulk acoustic resonator (FBAR), an acoustic decoupler formed on the bottom FBAR, and a top FBAR formed on the acoustic decoupler. Each FBAR has a bottom electrode, a piezoelectric layer formed on the bottom electrode, and a top electrode formed on the piezoelectric layer. The decoupling layer capacitance arising between the two electrodes enclosing the acoustic decoupler in a CRF is configured to achieve targeted filter response. A compensating capacitance is introduced to improve the amplitude and phase imbalance performance of an unbalanced to balanced CRF by eliminating the existence of asymmetric port-to-ground or feedback capacitance at the balanced output port produced by the decoupling layer capacitance.

New designs for multilayer ceramic capacitors are described with high voltage capability without the need of coating the part to resist surface arc-over. One design combines a high overlap area for higher capacitance whilst retaining a high voltage capability. A variation of this design has increased voltage capability over this design as well as another described in the prior art although overlap area and subsequently capacitance is lowered in this case. These designs are compared to the prior art in examples below.

A semiconductor integrated circuit having a built-in PLL circuit which has two charge pump circuits for charging and discharging capacitive elements of a loop filter in response to signals generated by a phase comparator circuit. One of the two charge pump circuits has current sources which generate current values smaller than those generated by current sources of the other charge pump circuit. The loop filter has a first capacitive element connected to a charge/discharge node, and a second capacitive element connected to the charge/discharge node through a resistive element. The first capacitive element is charged and discharged by the one charge pump circuit, while the second capacitive element is charged and discharged by the other charge pump circuit. A charging current source of the one charge pump circuit operates simultaneously with a discharging current source of the other charge pump circuit, i.e., the charge pump circuits operate in opposite phase.

The present invention discloses an energy-feedback type power quality disturbance generating device, which relates to a power quality disturbance generating device. The device comprises a harmonic source (1), a feedback link (2), a middle direct current capacitor (3), a control terminal (4), a first LCL filtering link (5), and a second LCL filtering link (6). The control terminal (4) adopts a DSP controller to realize that a control signal which is generated according to the setting of a user controls the harmonic source to partially generate current disturbance. The harmonic source and the feedback link are cascaded via the middle direct current capacitor to form an AC-DC-AC topological structure so as to realize power feedback. The alternating current side of the harmonic source is connected with a power network via the first LCL filtering link. The alternating current side of the feedback link is connected with the power network via the second LCL filtering link. The device is capable of simulating harmonic current, active current, inductance reactive current or capacitive reactive current of a plurality of combination frequencies, and the device is capable of simulating various working conditions of a plurality of nonlinear loads such as electric arc furnaces, medium frequency furnaces, welding machines and frequency converters, etc.

The invention relates to an amorphous silicon image sensor with a storage capacitor structure, comprising a plurality of pixel units. Each pixel unit comprises a grid wiring, a first insulating layer, an active layer, a data wiring, a second insulating layer, a storage capacitor, a photosensitive diode, a passivation layer and a bias voltage wire, wherein the storage capacitor is arranged below the photosensitive diode; a lower electrode of the storage capacitor is formed on a glass substrate or the first insulating layer, and an upper electrode of the storage capacitor is formed on a dielectric layer and connected with a source electrode; a first electrode of the photosensitive diode is in co-electrode with the upper electrode of the storage capacitor; and a second electrode of the photosensitive diode is conductive with the lower electrode of the storage capacitor and the bias voltage wire. By means of the amorphous silicon image sensor disclosed by the invention, the charge storagecapacity of the pixel units is increased under the condition of not enlarging or reducing pixel dimensions by arranging the storage capacitor below the photosensitive diode, and therefore the purposeof enhancing the signal dynamic range of a thin film transistor matrix panel under the precondition of not losing the resolution ratio of the thin film transistor matrix panel is achieved.

In an antenna apparatus, two pattern antennas are arranged side by side in an area close to a ground conductor layer on a surface of a dielectric substrate, in such a manner as to be formed substantially line-symmetrical with each other. Each of the pattern antennas includes a radiation element having a feed coupler, a mutual coupler, and a feed element fed by a high frequency circuit unit. An open end of the radiation element is located near the ground conductor layer. The feed element and the feed coupler are capacitively coupled with each other, whereby the radiation element is excited. At the excitation, the mutual couplers that extend substantially in parallel with and close to each other are capacitively coupled with each other, and hence, polarization planes of the electric fields radiated from the radiation elements can be made orthogonal to each other.

A system and/or method for sensing the presence of moisture (e.g., rain) and/or other material(s) on a window such as a vehicle window (e.g., vehicle windshield, sunroof or backlite). In certain example embodiments of the invention, at least one sensing capacitor is supported by a window such as a vehicle windshield, the capacitor(s) having a field that is affected by moisture (e.g., rain) on a surface of the window. A sensing circuit outputs an analog signal that is based on and/or related to the capacitance(s) of the sensing capacitor(s). The analog output of the circuit may be converted to a digital signal via sigma-delta modulation, and subjected to processing (e.g., correlation) for determining whether moisture (e.g., rain, dew, fog, etc.) or the like is present on the surface of the window.

A silicon on insulator shaped structure formed to reduce floating body effect comprises a T-shaped active structure and a body contact for back bias. Etching a T-shape through two layers of oxide will form the T-shaped active areas. A back bias is formed when a metal line is dropped through the SOI structure and reaches a contact plug. This contact plug is doped with N+ or P+ dopant and is embedded in a Si substrate. The T-active shaped structure is used to reduce the short channel effects and junction capacitance that normally hinder the effectiveness of bulk transistors. The back bias is used as a conduit for generated holes to leave the SOI transistor area thus greatly reducing the floating effects generally associated with SOI structures.

The invention discloses a flexible piezoelectric three-dimensional tactile sensor array which comprises a PDMS semispherical projection layer, an upper electrode layer, a nanometer structure piezoelectric film layer, a lower electrode layer and a printed circuit board flexible substrate layer, wherein the PDMS semispherical projection layer, the upper electrode layer, the nanometer structure piezoelectric film layer, the lower electrode layer and the printed circuit board flexible substrate layer are successively connected from top to bottom. The nanometer structure piezoelectric film layer isa nano structure ZnO piezoelectric film and is arranged between the upper electrode layer and the lower electrode layer which are arranged in an array pattern manner, thereby forming a plurality of piezoelectric sensitive units. The three-dimensional tactile sensor array is composed of M*N separated sensor units. Each sensor unit comprises a PDMS semispherical projection and three piezoelectric sensitive capacitors. The PDMS semispherical projection transmits a three-dimensional contact force to the three piezoelectric sensitive capacitors. Through the magnitude of charges which are generatedby the three piezoelectric sensitive capacitors, the external three-dimensional contact force is measured. The invention further discloses a preparation method of the flexible piezoelectric three-dimensional tactile sensor. The flexible piezoelectric three-dimensional tactile sensor array has advantages of three-dimensional contact force measurement, high sensitivity, high flexibility and high dynamic response.

Embodiments of the invention provide a brake pad and a thickness detection method, and belong to the field of an automobile brake system. The brake pad comprises a backboard, a thermal insulation layer, a friction block, and lead-out wires, the backboard is connected with the thermal insulation layer through the friction block, the friction block is provided with a groove, metallization processing is performed on a first sidewall of the groove to form a first electrode layer, metallization processing is performed on a second sidewall of the groove to form a second electrode layer, the lead-out wires comprise a first leading wire and a second leading wire, the first leading wire is electrically connected with the first electrode layer, and the second leading wire is electrically connected with the second electrode layer. According to the brake pad, the capacitance between the first electrode layer and the second electrode layer is acquired in real time, the thickness change of the brake pad is obtained through the change of the capacitance, the abrasion state of the brake pad is obtained in real time through the thickness change of the brake pad, drivers can maintain and replace the brake pad in advance, and hidden risks during driving can be reduced.

In a touch-mode capacitance type pressure sensor, a quartz pressure sensor that can solve difficulty in thickness control on a diaphragm due to a low etching precision which is a drawback in a pressure sensor using a detecting piece made from silicon, and deterioration in a detecting accuracy and poor repetitive reproducibility in elastic deformation due to the difficulty, respectively, is provided by utilizing quartz as a detecting piece for the pressure sensor. The quartz pressure sensor includes a bottom plate made from an insulating material, a lower electrode film and a dielectric film sequentially laminated on a face of the bottom plate, a detecting piece provided at a position thereof opposed to said dielectric film with a thin portion and fixed on the face of the bottom plate, and an upper electrode film formed in at least one portion of the thin portion having a positional relationship thereof opposed to the lower electrode film, in which a fine gap airtight space is provided between a lower face of the detecting piece and the dielectric film is characterized in that the detecting piece is made from a quartz material.

A temperature sensing circuit using CMOS switch-capacitor includes a PNP BJT, a hysteresis comparator, a transconductance amplifier, two current sources, two capacitors, and six switches. A voltage complementary to the absolute temperature (CTAT) is generated according to the PNP BJT, and a voltage proportional to the absolute temperature (PTAT) is generated according to two capacitors and the transconductance amplifier. When the voltage proportional to absolute temperature is greater than the voltage complementary to absolute temperature as the temperature rising, the hysteresis comparator outputs a high level signal.

The invention relates to a tiled grating displacement error monitoring system, which comprises a grating tiling device for mounting a tiled grating, wherein a fine adjuster platform of the grating tiling device is provided with a piezoceramics driver; two polar plates of a first digital capacitance micro-displacement sensor are oppositely arranged on positions in the horizontal direction of a coarse adjuster platform and a lower platform of the fine adjuster respectively; two polar plates of a second digital capacitance micro-displacement sensor are oppositely arranged on positions perpendicular to the lower platform and an upper platform of the fine adjuster respectively; output ends of the first and second digital capacitance micro-displacement sensors are connected with the input end of a signal sample circuit; the output end of the signal sample circuit is connected with the input end of a controller of a singlechip; the output end of the singlechip is connected with a PC through a serial port communication circuit; and the output end of the PC is connected with the control end of the piezoceramics driver through a D/A converter.

A source-drain voltage of one of two transistors connected in series becomes quite small in a set operation (write signal), thus the set operation is performed to the other transistor. In an output operation, two transistors operate as a multi-gate transistor, therefore, a current value can be small in the output operation. In other words, a current can be large in the set operation. Therefore, the set operation can be performed rapidly without being easily influenced by an intersection capacitance and a wiring resistance which are parasitic on a wiring and the like. Further, an influence of variations between adjacent ones can be small as one same transistor is used in the set operation and the output operation.

The invention discloses a sampling hold circuit which comprises a clock generation sub-circuit, a grid voltage bootstrap unit and a sampling hold sub-circuit, wherein the clock generation sub-circuit is provided with a first output end and a second output end, the first output end and the second output end are both connected with the grid voltage bootstrap unit, the sampling hold sub-circuit comprises a sampling switch and a holding capacitor, and the grid voltage bootstrap unit is further connected with an external power supply and the sampling switch. The sampling hold circuit further comprises a leak-proof sub-circuit which is connected between a bootstrap capacitor of the grid voltage bootstrap unit and the ground, and the leak-proof sub-circuit is further connected with the clock generation sub-circuit and the external power supply. When the sampling hold sub-circuit is switched from a hold mode to a sampling mode, the bootstrap capacitor and the ground are disconnected by the leak-proof sub-circuit. According to the sampling hold circuit, leakage of electric charge on the bootstrap capacitor in a hold and sampling switching process is effectively prevented, and reducing of bootstrap voltage is prevented, and the degree of linearity of the sampling switch is guaranteed.

A semiconductor integrated circuit device including a dynamic random access memory (DRAM) unit having improved signal-to-noise ratio, reduced bit line capacitance, and reduced area is provided. The DRAM unit includes a plurality of bit line pairs, each bit line pair including a first metal conductor and a second metal conductor. Each bit line pair includes a reference bit line and a sense bit line. Each bit line pair may be configured such that the reference bit line and the sense bit line are longitudinally oriented with respect to each other. Alternatively, each bit line pair is configured such that the first metal conductor and the second metal conductor are symmetrically twisted about each other in at least one location. The lateral spacing between a cell plate and a transistor gate is minimized, resulting in reduced overall area.

Disclosed herein is a semiconductor-device manufacturing method including the steps of: computing a capacitance, a resistance as well as capacitance and resistance variations as quantities generated as a result of changing the physical layout of a semiconductor integrated circuit in a range determined in advance; dividing the physical layout of the semiconductor integrated circuit into functional blocks and analyzing the physical layout in the functional-block units; computing signal delays for each of the functional blocks from the computed capacitance, the computed resistance as well as the computed capacitance and resistance variations and from a delay table provided for element and wire sections of each of the functional blocks; and finding signal delays in all the functional blocks composing the semiconductor integrated circuit on the basis of the signal delay computed for each of the functional blocks and the basis of a result of the analysis carried out on the physical layout.

This invention provides an internal formation method for pole plates of lead acid batteries including a first stage of several times of alternate charge and discharge, in which, the charge current is 0.13-0.27C/A, the total charge time is 35-55 hours, the discharge current is 0.13-0.27C/A, the discharge time is 0.5-4.5 hours, the battery is put at rest for 0-3 hours after the first stage then to be discharged according to the capacitance then the second stage of charge is done and the charge current is 0.02C-0.1C/A, the total time is 18-21 hours, in which, C expresses the rating volume of the battery.