4 results about "Breakdown voltage" patented technology

The invention discloses a power semiconductor device and a manufacturing method thereof. The power semiconductor device comprises a substrate, a core forming layer, a buffer layer, a channel layer, a barrier layer, a source electrode, a drain electrode, a grid electrode and a junction termination structure located on the barrier layer. The junction termination structure extends in the direction from the edge, close to one side of the drain electrode, of the grid electrode to the drain electrode. Due to the piezoelectric effect caused by lattice constant difference between the junction termination structure and the barrier layer under the junction termination structure, two-dimensional electronic gas at the position of the interface of the barrier layer and the channel layer is partially exhausted. The junction termination structure can effectively improve the electric field distribution of the barrier layer so as to improve the breakdown voltage of the device.

A nitride semiconductor power device includes an AlGaN multilayer, which has changeable Al composition along a depositing direction, and Si_xNy layer, so as to minimize an increase in a leakage current and a decrease in a breakdown voltage, which are caused while fabricating a heterojunction type HFET device. A semiconductor device includes a buffer layer, an AlGaN multilayer formed on the buffer layer, a GaN channel layer formed on the AlGaN multilayer, and an AlGaN barrier layer formed on the AlGaN multilayer, wherein aluminum (Al) composition of the AlGaN multilayer changes along a direction that the AlGaN multilayer is deposited.

The invention relates to a production method of a metal wiring structure, comprising the following steps: providing a semiconductor substrate and a metal interlevel dielectric layer positioned on the semiconductor substrate; forming an interconnect structure in the metal interlevel dielectric layer; treating the interconnect structure with plasma; forming a etch barrier layer on the interconnect structure. With the methods of the invention adopted, the electron migration between the adjacent interconnect structures is avoided, the binding force between the metal interlevel dielectric layer and the etch barrier layer is increased, the breakdown voltage between the adjacent interconnect structures in integrated circuits is increased and the leakage current is reduced.