29 results about "CMOS" patented technology

Integrating high-voltage devices with other circuitry, which may be fabricated on a semiconductor wafer using low-voltage foundry technology, such as a low-voltage complementary metal oxide semiconductor (LV-CMOS) process. The other circuitry may include low-voltage devices, such as switching transistors used in logic circuits, computer circuitry, and the like, or other high-voltage devices, such as a microelectromechanical system (MEMS) switch. The high-voltage devices may be used to create useful high-voltage circuits, such as level-shifting circuits, input protection circuits, charge pump circuits, switching circuits, latch circuits, latching switch circuits, interface circuits, any combination thereof, or the like. The high-voltage circuits may be controlled by the other circuitry.

A system has a reduced sensitivity to Single Event Upset and/or Single Event Transient(s) compared to traditional logic devices. In a particular embodiment, the system includes an input, a logic block, a bias stage, a state machine, and an output. The logic block is coupled to the input. The logic block is for implementing a logic function, receiving a data set via the input, and generating a result f by applying the data set to the logic function. The bias stage is coupled to the logic block. The bias stage is for receiving the result from the logic block and presenting it to the state machine. The state machine is coupled to the bias stage. The state machine is for receiving, via the bias stage, the result generated by the logic block. The state machine is configured to retain a state value for the system. The state value is typically based on the result generated by the logic block. The output is coupled to the state machine. The output is for providing the value stored by the state machine. Some embodiments of the invention produce dual rail outputs Q and Q′. The logic block typically contains combinational logic and is similar, in size and transistor configuration, to a conventional CMOS combinational logic design. However, only a very small portion of the circuits of these embodiments, is sensitive to Single Event Upset and/or Single Event Transients.

The invention discloses a CMOS image sensor dual-mode communication receiving system of an integrated photoelectric detector. The system comprises a CMOS image sensor of the integrated photoelectric detector, a 01 picture generation module, a threshold value generation module, a light source detection module, a gray image generation module, a high-speed communication signal processing module and a low-speed communication signal processing module. The CMOS image sensor of the integrated photoelectric detector outputs an image signal, a mark picture is generated through self-feedback by employing the threshold value generation module, the gray image generation module and the 01 picture generation module, a detected light source position is fed back to the CMOS image sensor of the integrated photoelectric detector via the light source detection module, a received communication signal is processed via the high-speed communication signal processing module and the low-speed communication processing module, high-speed communication information and low-speed communication information are outputted, and the reception of dual-mode communication is realized. According to the system disclosed by the invention, the accuracy of light source detection is effectively improved; and the system can be used in visible light communication.

An optical device may include a sacrificial limiter filter including at least one layer of graphene disposed on a substrate. The at least one layer of graphene may be configured to absorb and scatter at least a portion of electromagnetic radiation incident on the at least one layer of graphene.

A TTL and CMOS compatible type input buffer comprises a reference voltage generator and an input buffer which comprises at least one stage input invertor which include a PMOS tube P1 and an NMOS tube N2, the grids of which are connected as an input end for inputting signal Vin, a source pole of the PMOS tube P1 is connected with a reference voltage VREF provided by the reference voltage generator; when the circuit works in the TTL mode, the reference voltage generator provides reference voltage VREF for the input invertor between 3.3 and 3.5 V, the turning point voltage of the input invertor is 1.4 V to make input noise margin maximum; when the circuit works in the CMOS mode, the reference voltage generator has no quiescent power dissipation, the reference voltage generator provides reference voltage VREF for the input invertor between 4.6 and 5 V, the turning point voltage of the input invertor is 2.5 V to obtain the maximum noise margin.

The invention relates to a voltage reference circuit. Aiming at the problems that an existing reference circuit needs resistors and is high in technology requirement and large in power consumption, a low power consumption non-resistor full CMOS voltage reference circuit is provided. According to the technical scheme, the low power consumption non-resistor full CMOS voltage reference circuit comprises a bias current module, a positive temperature voltage module, a negative temperature voltage module and a voltage superposition module. Voltage superposition is used for outputting voltage reference, and the temperature coefficient of the voltage reference is reduced through selection of filed effect transistor structural parameters. According to the low power consumption non-resistor full CMOS voltage reference circuit, power consumption is low, the resistors are not needed, any type of bipolar transistors are not needed either, and the integrated circuit can be manufactured by the adoption of a standard CMOS technology, so that the application range and flexibility are obviously improved.

The invention discloses an interface level switch device. The interface level switch device is arranged on a main board and is used for detecting serial port signals and outputting level signals corresponding to a main board serial port controller of a serial port controller. The interface level switch device comprises a detecting module, a circuit switching module and an RS232 level conversion module, wherein the detecting module is used for detecting the serial port input signals so as to judge the type of the serial port input signals and outputs corresponding control signals according to judgment results; the circuit switching module comprises a logic control pin, an input end, a first group of output ends and a second groups of output ends, and the logical control pin receives the control signals sent by the detecting module and makes the input end selectively judge whether the serial port input signals are output from the first output ends or the second output ends; the RS232 level conversion module is connected with the first group of output ends of the circuit switching module and is used for converting RS232 serial port signals into CMOS signals and outputting the CMOS signals to the main board serial port controller.

A process for forming a void-free dielectric layer is disclosed in which adjoining gate film stacks are formed on a semiconductor substrate. Each gate film stack includes a silicide layer and a hard mask that overlies the silicide layer. A first selective etch is performed so as to reduce the width of the hard mask on each of the gate film stacks, exposing portions of the top surface of the silicide layer. A second selective etch is then performed to reduce the width of the silicide layer. Spacers are then formed on opposite sides of each of the gate film stacks, and a dielectric film is formed that extends over the gate film stacks. By reducing the width of the hard mask layer and the silicide layer, gate film stacks are obtained that have reduced width near the top of each gate film stack, preventing voids from forming in the dielectric film.

The invention provides a semiconductor device structure and a method for manufacturing the same, wherein the method is characterized in merging a high dielectric constant/metal gate core device and a SiON/polysilicon gate input-output device. In the sub 45 nanometers CMOS (complementary metal oxide semiconductor) technology, when the SiON/polysilicon gate technology is used for the input-output device, the high dielectric constant/metal gate is adopted for the core device. According to the method provided by the invention, the traditional SiON/polysilicon gate input-output device and the high dielectric constant/metal gate core device can be merged effectively, thus the integral performances of the semiconductor device can be improved, and the technology process can be simplified.

The invention relates to a subthreshold latch, which comprises a master latch structure and a slave latch structure, wherein the master latch structure and the slave latch structure are provided with two input ends, namely a data input end D and a clock input end clk, and are also provided with an output end Q; the master latch consists of inverters I1, I2 and I3 and complementary metal oxide semiconductor (CMOS) transmission gates T1 and T2; the slave latch consists of inverters I4, I5 and I6 and CMOS transmission gates T3 and T4; one path of the clock input end clk is connected with an inverter I7 and is input to the master latch and the slave latch respectively, and the other path of the clock input end clk is directly input to the master latch and the slave latch; and the transmission gates are arranged in feedback loops of the master latch and the slave latch, so that the subthreshold latch can operate effectively under the condition of subthreshold. The subthreshold latch has high anti-interference capacity, and low power consumption.

This invention relates to a method for making a high-linearity and high-power CMOS structure and particularly to a field plate technology that is applied to a CMOS component, in which the field plate is formed on a dielectric layer of the CMOS, being arranged above a gate and a drain. An electric field is provided to significantly improve the RF linearity and output power of the CMOS component.

The invention discloses a power detection circuit in a radio frequency front-end chip. The radio frequency front-end chip has an MIPI control module. The power detection circuit comprises a delay circuit and a comparator. The delay circuit is used for generating a following voltage lagging behind a power supply voltage of the radio frequency front-end chip during the power-on process of the radiofrequency front-end chip. The comparator compares the following voltage with a comparison threshold voltage and sends a reset signal to the MIPI control module. Compared with the power detection circuit in an existing radio frequency front-end chip, the power detection circuit in the invention saves a reference voltage circuit, thereby reducing chip area occupied by the power detection circuit andreducing chip manufacturing cost. Besides, all devices in the delay circuit are realized based on CMOS technology, so that chip occupation area is small; and the comparator is realized through the asymmetric phase inverter, thereby reducing or even avoiding static working current and reducing energy consumption.

The invention relates to a portable Chinese-sensible code reading machine and a reading method thereof. The reading machine comprises a housing, a display screen, a CMOS camera, a loudspeaker, a switch and a reading circuit. The reading circuit comprises an ARM embedded processor, an NAND memory unit, a FLASH memory, a WIFI module, a 3G module and a USB interface. The ARM embedded processor is respectively connected with the NAND memory unit, the FLASH memory, the WIFI module, the 3G module and the USB interface I/O. The reading method comprises a character database. The database can prevent a system operation speed from being reduced due to a complex coding conversion process, and ensures coding accuracy at the same time. The reading machine and the reading method provided by the invention have the advantages of accurate and rapid Chinese-sensible code reading, high anti-interference capability, high scalability, simplicity, easy use and good portability, thereby being suitable for Chinese-sensible code reading application on multiple occasions.

The invention discloses an infrared LED finger vein collecting device with adjustable brightness, and belongs to the technical field of finger vein collection. The infrared LED finger vein collectingdevice comprises a box body, a finger fixator, a DSP controller, digital potentiometers and infrared light source arrays. Installation slots are arranged at the top of the box body. The infrared lightsource arrays are installed in the respective installation slot through lifting handles. The digital potentiometers are arranged on the lifting handles. Interface slots are arranged at the side of the box body. Laying grooves are arranged between the interface slots and the installation slots. Arc grooves are arranged between the laying grooves and the installation slots. Spiral adjustment knobsare arranged at the side of the box body. The invention solves the problem that the image of the finger vein collected by using a common light source in the prior art is unclear and cannot meet the requirement, can adjust the position of the finger relative to a CMOS camera and the infrared light source arrays, and is convenient for finger vein image collection.

The invention discloses an absolute capacitor and differential capacitor measuring circuit and method. The absolute capacitor and differential capacitor measuring circuit comprises a crystal oscillation circuit for measuring an absolute capacitor and a circuit for measuring a differential capacitor, and the absolute capacitor and differential capacitor measuring method comprises a method for measuring the absolute capacitor and a method for measuring the differential capacitor. According to the absolute capacitor and differential capacitor measuring circuit, the principle of the crystal oscillation circuit is utilized, all elements are common electronic elements, the structure is simple, the floor area of the circuit is small, and the elements are convenient to purchase, low in power consumption and extremely low in cost; a single power supply is adopted for supplying electricity to the circuit, voltage of a VCC of the power supply ranges from 2V to 6V, a TTL and a CMOS level are completely compatible, and the circuit has a wider application range; the resolution of the circuit mainly depends on frequency measurement precision, an existing frequency measurement technology is mature, and high-precision capacitance measurement can be achieved; according to the circuit for measuring the differential capacitor, a frequency difference is extracted only by using a data flip-flop; the circuit for measuring the differential capacitor is simple and can be used for measuring not only the differential capacitor but also the absolute capacitor.

A circuit and method for reducing metastability of a CMOS SR flip flop is provided. The circuit comprises a first switching module and a second switching module that are operatively coupled to a first and second output terminal of the CMOS SR flip-flop. The method includes injecting current onto the first and second output terminals of the CMOS SR flip-flop at mutually opposite directions during permissible mid-range voltages of the output terminals. Further, the method includes driving the output terminals of the CMOS SR flip-flop into the predetermined state of zero and predetermined stable state of Vdd by utilizing the currents injected onto the output terminals. As a result, the metastable point of the CMOS flip-flop is diverted from the corresponding metastable voltage and thereby reduces the metastability of the CMOS SR flip-flop.

Embodiments relate to a circuitry for digital data communication. The circuitry includes an inverter circuit connected between an input node and an output node. The inverter circuit has core circuits each of which includes a complementary metal-oxide-semiconductor (CMOS) transistor of a first type and a CMOS transistor of a second type having a first common gate node connected to the input node and a first common drain node connected to the output node. The circuitry further includes another inverter circuit of a switching threshold voltage different than that of the inverter circuit and connected between the input node and the output node. The other inverter circuit has core circuits each of which includes a CMOS transistor of a third type and a CMOS transistor of a fourth type having a second common gate node connected to the input node and a second common drain node connected to the output node.

A thermal infrared sensor array in a wafer-level package includes at least one infrared-sensitive pixel produced using silicon micro mechanics, comprising a heat-isolating cavity in a silicon substrate surrounded by a silicon edge, and a thin membrane connected to the silicone edge by of thin beams. The cavity extends through the silicon substrate to the membrane, and there are slots between the membrane, the beams and the silicon edge. A plurality of infrared-sensitive individual pixels are arranged in lines or arrays and are designed in a CMOS stack in a dielectric layer, forming the membrane, and are arranged between at least one cover wafer which is designed in the form of a cap and has a cavity and a base wafer. The cover wafer, the silicon substrate and the base wafer are connected to one another in a vacuum-tight manner and enclosing a gas vacuum.

The invention relates to an ion implantation method of a P-type well, a P-type well structure and a CMOS device manufacturing method, and relates to the semiconductor integrated circuit manufacturingprocess. In the ion implantation process of the P-type well structure, the carbon ion implantation process is added between the well inhibition punch-through ion implantation process and the thresholdvoltage adjustment ion implantation process, so an amorphous layer of a carbon ion implantation layer is formed between an inhibition punch-through ion implantation layer and a threshold voltage adjustment ion implantation layer. The amorphous layer can inhibit ions of the inhibition punch-through ion implantation layer from diffusing to the threshold voltage adjustment ion implantation layer, the concentration of the shallowly-doped side of a PN junction is kept unchanged, and increase of parasitic capacitance of the PN junction is prevented.

The invention provides a structure of a planer phase change memory storage unit and a manufacturing method of the planer phase change memory storage unit. The structure of the planer phase change memory storage unit and the manufacturing method of the planer phase change memory storage unit solve the problem of compatibility of a phase change storage unit in an existing phase change memory and a CMOS logic process, use a physical gas-phase deposition technology, and omit the step of manufacturing a heating electrode. In the manufacturing process of the planer phase change memory storage unit, a metal organic chemical gas-phase deposition technology or atom layer deposition technology with quite high cost does not need to be adopted to grow phase-change materials, and good performance can be achieved only through the ordinary physical gas-phase deposition technology. Besides, compared with the CMOS logic process, only one mask is added in the entire manufacturing process, production cost and manufacturing difficulty are largely lowered, and influence on circuit performance is avoided for CMOS transistors.

A method for forming a gate structure of a 3D memory device is provided. The method comprises forming an array wafer including a periphery region and a staircase and array region. A process of forming the array wafer comprises forming an array well structure in a first substrate in the periphery region, forming an array device on the first substrate in the staircase and array region, and forming at least one vertical through contact in the periphery region and in contact with the array well structure. The method further comprises forming a CMOS wafer, and bonding the array wafer and the CMOS wafer. The method further comprises forming at least one through substrate contact penetrating the first substrate and the array well structure, and in contact with the at least one vertical through contact.

The invention provides an ESD protection transistor and an ESD protection method of a CMOS device. The ESD protection transistor comprises a substrate, a buried dielectric layer and a surface semiconductor layer, wherein the buried dielectric layer is formed on the substrate, and the surface semiconductor layer is formed on the buried dielectric layer; an open data link interface transistor is formed in the surface semiconductor layer. On the basis of the structural design of the ESD protection transistor, the protection capability of the transistor is improved, so that effective ESD protection is carried out on the CMOS device, and the problems of damage, failure or performance reduction of the CMOS device caused by ESD are avoided.

The invention discloses a CMOS making method. The method comprises steps: a substrate is etched to form a first fin and a second fin extending along a first direction; a pseudo gate stack extending along a second direction is formed on the first fin and the second fin; source and drain areas are formed at two sides of the pseudo gate stack in the first fin and the second fin along the first direction; the pseudo gate stack is removed, and a first gate opening and a second gate opening for exposing the first fin and the second fin are left in a first area and a second area; one part of the first fin in the first area is removed, and the first opening is left; epitaxial growth of a first channel layer is carried out in the first opening; one part of the second fin in the second area is removed, and the second opening is left; epitaxial growth of a second channel layer is carried out in the second opening; and a gate stack extending along the second direction is formed on the first channel layer and the second channel layer. According to the CMOS making method of the invention, epitaxy of a different-material high-mobility channel layer is carried out selectively step by step, and the mobility and the driving capacity of device carriers can be improved in a low cost and high efficiency mode.

The invention relates to the technical field of scientific-grade CMOS cameras, in particular to a diffuse reflection structure of a scientific-grade CMOS camera and a processing method and equipment of the diffuse reflection structure. The outer surface of the assembly part arranged on one side of the imaging mechanism is designed to be the spark pattern surface, so that light passing through the spark pattern surface of the assembly part is affected by the rough surface, the light is prevented from being reflected and condensed on the surface, the requirement of diffuse reflection is met, and the imaging quality is improved. The invention further provides processing equipment and a processing method of the diffuse reflection structure of the scientific-grade CMOS camera, an assembly part with a smooth surface originally can be processed into an assembly part with spark patterns on the surface through the processing equipment or the processing method, and the diffuse reflection structure is simple in structure and easy to process.