CMOS making method

A manufacturing method and fin technology, which are applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve the problems of reducing device reliability, cross-interference, unfavorable local device and CMOS hybrid integration in circuits, etc. cost effect

Active Publication Date: 2017-04-05
INST OF MICROELECTRONICS CHINESE ACAD OF SCI
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

The technical effect of this patented technology allows for better choice between material choices by growing layers on specific areas within each step during fabrication process instead of just one area at once. This results in lower costs compared to traditional methods while also improving performance due to increased carrier movement and drive capabilities.

Problems solved by technology

Technological Problem: Current methods used to fabricate tri-gate type transistors are complex processes requiring multiple layers of dielectric films and highly mobile dopants like germanium, gallium arsenic, indanthrosonia carboxylidene chloroimides, etc., leading to increased complexity during processing and reduced efficiency when forming thin film gates over these structures.

Method used

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Embodiment Construction

[0021] The features and technical effects of the technical solution of the present invention will be described in detail below with reference to the accompanying drawings and in conjunction with schematic embodiments, disclosing a high-mobility FET-type CMOS manufacturing method that improves device driving capability and reliability at low cost and high efficiency. It should be pointed out that similar reference numerals represent similar structures, and the terms "first", "second", "upper", "lower" and the like used in this application can be used to modify various device structures or manufacturing processes . These modifications do not imply spatial, sequential or hierarchical relationships of the modified device structures or fabrication processes unless specifically stated.

[0022] In particular, the following figure A is a cross-sectional view along a direction perpendicular to the channel (along the second direction), and certain figure B is a cross-sectional view along

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Abstract

The invention discloses a CMOS making method. The method comprises steps: a substrate is etched to form a first fin and a second fin extending along a first direction; a pseudo gate stack extending along a second direction is formed on the first fin and the second fin; source and drain areas are formed at two sides of the pseudo gate stack in the first fin and the second fin along the first direction; the pseudo gate stack is removed, and a first gate opening and a second gate opening for exposing the first fin and the second fin are left in a first area and a second area; one part of the first fin in the first area is removed, and the first opening is left; epitaxial growth of a first channel layer is carried out in the first opening; one part of the second fin in the second area is removed, and the second opening is left; epitaxial growth of a second channel layer is carried out in the second opening; and a gate stack extending along the second direction is formed on the first channel layer and the second channel layer. According to the CMOS making method of the invention, epitaxy of a different-material high-mobility channel layer is carried out selectively step by step, and the mobility and the driving capacity of device carriers can be improved in a low cost and high efficiency mode.

Description

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Claims

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Application Information

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Owner INST OF MICROELECTRONICS CHINESE ACAD OF SCI
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