7 results about "Gate dielectric" patented technology

The invention provides a method for manufacturing a flash memory. The method comprises the following steps of: providing a substrate, wherein a plurality of isolation structures are arranged on the substrate, and a dielectric layer and a floating gate are arranged on the substrate among the isolation structures; forming a mask layer on the substrate to cover the isolation structures in a peripheral area and the isolation structures which are positioned in a memory area and are adjacent to the peripheral area; removing one part of the isolation structures in the memory area by taking the mask layer as a mask, so that the first height difference between the surfaces of the isolation structures in the peripheral area and the surface of the dielectric layer and between the surfaces of the isolation structures which are positioned in the memory area and are adjacent to the peripheral area and the surface of the dielectric layer exists, and the second height difference which is less than first height difference exists between the surfaces of the rest isolation structures in the memory area and the surface of the dielectric layer; removing the mask layer; forming a gate dielectric layer on the substrate; and forming a conductor layer on the substrate. The flash memory manufactured by the method has high-grid coupling efficiency and excellent electrical property.

The invention provides a flash memory device and a formation method thereof. The flash memory device comprises a semiconductor substrate, a plurality of floating gates, control gate dielectric layers, control gates, and selection gates, wherein the semiconductor substrate comprises a plurality of first regions parallel to each other and second regions located at one ends of the first regions; the plurality of floating gates are located on the first regions of the semiconductor substrate, and a first opening is formed between the adjacent floating gates; the control gate dielectric layers are located on the sidewalls and the bottoms of the first opening and the surfaces of the floating gates; the control gates are located on the control gate dielectric layers to fully fill in the first openings; the selection gates are located on the second regions of the semiconductor substrates; the top surfaces of the selection gates are flush with the bottom surfaces of the control gates. The performance of the flash memory device is improved.

The invention provides a semiconductor structure and a preparation method thereof, a three-dimensional memory, a memory system and electronic equipment, relates to the technical field of semiconductor chips, and aims to improve the stability of the three-dimensional memory. The preparation method comprises the following steps: forming an initial laminated structure on one side of a substrate, wherein the initial laminated structure comprises gate replacement layers and initial gate dielectric layers which are alternately laminated; forming a channel hole; an initial channel structure is formed in the channel hole, the initial channel structure comprises a barrier layer and an initial charge storage layer which are arranged in sequence, and the barrier layer and the initial gate dielectric layer are different in etching rate under the same process condition; removing the initial gate dielectric layer to form a first gap; performing insulation processing on a target part of the initial charge storage layer through the first gap so as to convert the target part into an isolation part; and the first gap is filled with an insulating material. The semiconductor structure is applied to the three-dimensional memory so as to realize data reading and writing operation.