20 results about "Threshold voltage" patented technology

A method, system and memory controller are provided for implementing ECC (Error Correction Codes) control to provide enhanced endurance and data retention of flash memories. The memory controller includes a VT (threshold voltage) monitor to determine VT degradation of cells and blocks; the VT monitor configured to store information about the determined VT degradation; a first ECC engine having a first level of ECC capability; a second ECC engine having a second level of ECC capability, the second level higher than the first level, the second ECC engine having a longer latency than the first ECC engine; a logic to issue a read request to a particular cell/block, and, using the determined VT degradation, use the first ECC engine if the determined VT degradation is less than a threshold and to use the second ECC engine if the determined VT degradation is above the threshold.

An INVSRC node and a SAREF node are previously precharged. After a potential on a bit line is reset, the bit line (BLS node) is precharged. In this event, a clamp MOS transistor in a sense amplifier is in ON state, and an SA node is also precharged simultaneously. A precharge level is set to a value lower than a threshold voltage of an inverter. Subsequently, when SAEN transitions to “H,” a sense operation is performed. For reading data “0,” the SA node is rapidly increased to Vdd. For reading data “1,” the SA node slowly approaches to Vss. A change in the potential at the SA node is detected by the inverter.

A nonvolatile memory system includes a nonvolatile memory device including a plurality of memory cells; and a memory controller suitable for recovering normal data based on a recovery read level interval when an error occurs in the normal data read from the memory cells by using a reference read level, wherein the memory controller generates N distribution measurement values by measuring distribution values of threshold voltage levels of the memory cells at N respective distribution read levels, which have a preset read level interval with the reference read level serving as a center, and determines the recovery read level interval through calculating variations of the N distribution measurement values by using a linear equation, where ‘N’ is a natural number equal to or larger than 2.

A method for programming an MLC flash memory device minimizes interference between adjacent cells during a program operation, such that threshold voltage distribution becomes narrow and uniform. According to the method, an auxiliary program operation is performed on memory cells to be programmed, such that a majority of the memory cells have a positive threshold voltage. An LSB of a particular memory cell is programmed to a predetermined level, and data of the programmed LSB is sensed. An MSB of the particular memory cell is programmed to a predetermined level according to the sensed data of the LSB.

A design structure. The design structure includes: a first set of FETs having a designed first V_t and a second set of FETs having a designed second V_t, the first V_t different from the second V_t; a first monitor circuit containing at least one FET of the first set of FETs and a second monitor circuit containing at least one FET of the second set of FETs; a compare circuit configured to generate a compare signal based on a performance measurement of the first monitor circuit and of the second monitor circuit; a control unit responsive to the compare signal and configured to generate a control signal regulator based on the compare signal; and an adjustable voltage regulator responsive to the control signal and configured to voltage bias wells of FETs of the second set of FETs, the value of the voltage bias applied based on the control signal.

The invention relates to a lagging comparer, wherein it comprises current source I1, two input MOS tubes, three load MOS tubes, and lagging adjuster for adjusting the threshold value of comparer. When the input MOS tube is NMOS tube, the load MOS tube uses PMOS tube; the single threshold value of circuit is irrelative to the circuit element parameters, that one fixed input voltage of comparer can fix single threshold value; the inventive circuit has asymmetry positive feedback circuit to form the lagging circuit of lagging comparer, to generate threshold voltage and complete comparison. The invention also has positive feedback branch and output branch, MOS tube with static protection and resistance.

A method includes determining groups of rows to erase together in order to minimize the margin loss associated with bake after a large number of program and erasure cycles. The method alternatively includes determining groups of rows to erase together to minimize the width of a resultant erase threshold voltage distribution, erasing the groups together, stopping erasure of a group when the group is erase verified and performing the step of erasing on those groups which were not previously erase verified.

The invention discloses a light emitting diode (LED) drive circuit. The LED drive circuit comprises a transformer, a metal oxide semiconductor (MOS) tube, a power adjusting resistor, a direct current buffer circuit, a rectifying circuit and a voltage control circuit. When the voltage of a control end of the voltage control circuit is higher than of the threshold voltage of the MOS tube, breakover of the MOS tube is achieved, a current input by an external power supply passes by a first winding of the transformer, the MOS tube and the power adjusting resistor sequentially, and the rectifying circuit is powered on. When the voltage of the power adjusting resistor is similar to the voltage of a standard end of the voltage control circuit, the MOS tube is cut off, a second winding of the transformer charges a capacitor of the MOS tube through the direct buffer circuit, the rectifying circuit is powered on, and the first winding of the transformer supplies power to LED load through the rectifying circuit. When the capacitor voltage of the MOS tube is higher than the threshold voltage, breakover of the MOS is achieved again. The LED drive circuit can replace a power source to manage an integrated circuit (IC), simplifies the LED drive circuit and reduces the cost.

The invention belongs to the field of integrated circuit design, and particularly relates to a current source unit circuit of a current-steering digital analog converter. The current source unit circuit comprises a current source module, a switch module and a digital control module, wherein the current source module comprises a current source tube Mb2 and a current source tube Mb1, the digital control module comprises a first signal output end SWP and a second signal output end SWN, and the signals output by the first signal output end SWP and the second signal output end SWN are contrary. The switch module is formed by a control signal processing module and a control switch module. Via four MOS (metal oxide semiconductor) tubes including M1, M2, M3 and M4 which are particularly connected, variation amplitude of a control signal is reduced by about two threshold voltage, glitch of an output signal of the current-steering digital analog converter is reduced, dynamic performance is improved, and the current source unit circuit can be widely applied on the current-steering digital analog converter. Meanwhile, the utilization of a complementation control switch can also improve the glitch.

The invention includes a two terminal switching device having two stable resistivity values for each applied voltage, which when a voltage of not more than a first threshold voltage (Vth1) is applied, becomes in a first state having a higher resistivity, whereas when a larger second threshold voltage (Vth2) or more is applied, becomes in a second state having a lower resistivity; a resistance connected in series to the switching device; a terminal for applying a bias voltage (Vt) to both ends of a series circuit of the switching device and the resistance; a first pulse inputting terminal; and a second pulse inputting terminal. The invention provides a simple realization of a flip-flop circuit for a sequential logic circuit.

The invention discloses a protection circuit of a power switch tube and a load switch circuit. The protection circuit comprises a current-limiting protection circuit, an under-voltage protection circuit and an under-voltage short-circuit protection circuit, and the under-voltage short-circuit protection circuit is connected between the grid electrode of the power switch tube and the output end of the chip and used for lowering the grid electrode voltage of the power switch tube when the input voltage is under-voltage and the output voltage is smaller than the threshold voltage. Therefore, certain short-circuit protection can be provided for the power switch tube when the input voltage is under-voltage, and the power switch tube is prevented from being damaged when the output end of the chip is short-circuited.

The invention discloses a shift register, a gate drive circuit, a display device and a control method. The shift register comprises an input sub-circuit, a first control sub-circuit, a second control sub-circuit and an output sub-circuit. The input sub-circuit is connected with a first node and a second node, and controls the potentials of the first node and the second node according to an input signal and a first clock signal. The first control sub-circuit is connected with the first node and the second node and used for controlling the potential of the first node according to the potential of the second node and a second clock signal. The second control sub-circuit is connected with the first node, the second node and the third node, and is used for controlling the potential of the third node according to the potential of the first node, the potential of the second node, a second clock signal and an input signal. The output sub-circuit is connected with a first node, a third node, a first level end and a second level end, and can output a first output signal according to the potential of the third node. Therefore, the output abnormal phenomenon caused by positive bias of the threshold voltage of the transistor is avoided.