Multivalue memory storage with two gating transistors

Active Publication Date: 2009-04-16
S AQUA SEMICONDUCTOR LLC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Such sensing requires only two sense amplifiers, but sequential sensing imposes latency over concurrent sensing.
Because all four sense amplifiers must use a different reference voltage, implementation and manufacturing of such sense amplifiers is complex.

Method used

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  • Multivalue memory storage with two gating transistors
  • Multivalue memory storage with two gating transistors
  • Multivalue memory storage with two gating transistors

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Embodiment Construction

[0007]In the following detailed description, reference is made to the accompanying drawings which form a part hereof wherein like numerals designate like parts throughout, and in which are shown, by way of illustration, specific embodiments in which the invention may be practiced. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. Therefore, the following detailed description is not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims and their equivalents.

[0008]Embodiments of the present invention include a multivalue memory cell including two gating transistors arranged in parallel and a storage element such as a capacitor, onto which any one of four discrete voltages, or discrete voltage ranges, can be impressed; each voltage level or range of voltages may correspond in embodiments to a different data value repres...

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Abstract

Digital memory devices and systems, as well as methods of operating digital memory devices, that include a multivalue memory cell with a first and a second gating transistor arranged in parallel, having a first and a second node, respectively, coupled to a storage element, and sensing circuitry coupled to a third and a fourth node of the first and second gating transistors, respectively, to sense a stored voltage of the memory cell. In embodiments, the first and second gating transistors are configured to activate at different threshold voltage levels.

Description

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Claims

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Application Information

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IPC IPC(8): G11C11/40
CPCG11C11/56G11C2211/5642G11C2211/5634G11C11/565
Inventor RAO, G. R. MOHAN
Owner S AQUA SEMICONDUCTOR LLC
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