15 results about "Field-programmable gate array" patented technology

The invention provides an ultrasonic phased array detector with low power consumption and capability of real-timely transforming styles of arrays. The whole system comprises an FPGA (Field Programmable Gate Array) control module, a square MEMS (Micro-electromechanical Systems) ultrasonic sensing array, a PCI (Programmable Communications Interface) bus, a signal processing module and an array style and frequency selection module. The FPGA module comprises a pulse control unit and a beam control unit; the square MEMS ultrasonic sensing array is a square phased array with the same numbers of transverse rows and longitudinal rows which are made up of many MEMS ultrasonic sensors and have the same spacing; the array is formed by arranging a row of emission arrays and a row of receiving arrays in a crossing manner; each emission array element has an independent pulse excitation channel; each receiving array element has an independent echo receiving channel; the signal processing module is composed of amplification units and filter units, which have the same number with that of the receiving array elements; the array style and frequency selection module is composed of key arrays; the key arrays are capable of respectively representing many kinds of different array styles and different ultrasonic frequencies so as to be suitable for different detection conditions, thus a hardware structure of arrays is simplified; therefore, the ultrasonic phased array detector is applicable to detecting various robots under different special environments.

The invention discloses a wide-dynamic high-accuracy and edge time adjustable impulse wave producing method which is characterized by including the following steps: (1) arranging an impulse generator; (2) building an impulse wave model according to waveforms of impulse signals generated by the impulse generator; (3) determining the amplitude modulation position according to the impulse wave model built in the step (2); (4) arranging an amplitude modulator; (5) setting a field programmable gate array (FPGA) waveform processing unit; (6) arranging a state machine and a direct digital frequency synthesizer (DDS) cooperating with the state machine in work; and (7) leading the state machine and the direct digital frequency synthesizer to cooperate in work and leading details of impulse waveforms after fine adjustment to be completely displayed. The wide-dynamic high-accuracy and edge time adjustable impulse wave producing method uses the method of amplitude for time, leads impulse edges and impulse width to be subjected to wide-dynamic and high-accuracy adjustment completely through the digital measures, simplifies complexity of a signal source analog channel circuit, saves cost and reduces production debugging operation difficulty.

The invention discloses a detection circuit capable of detecting a plurality of arbitrary-combination keys by low cost, and a processing method. The detection circuit comprises control chips and a matrix key circuit, wherein the control chips include a single chip microcomputer, an MCU (Microprogrammed Control Unit), a CPLD (Complex Programmable Logic Device), an FPGA (Field Programmable Gate Array), an ARM (Advanced RISC Machine) and the like; each control chip is provided with R+C pieces of IO (Input/Output) pins; an R wire controls the IO as input and has an external interruption function;in addition, each IO pin has IO function settings, including floating, open-drain, push-pull, upward pull, downward pull and the like; and an AD (Analogue/ Digital) sampling functional or operationalamplifier, a comparator or a plug-in operational amplifier and a comparator are built in the controller chip. The detection circuit has the beneficial effects that no diodes are required, or only a small quantity of diodes is required to realize low-cost any-key no conflict and full-key no conflict, an audion MOS (Metal Oxide Semiconductor) tube and the like can be cooperated to realize IO reuse for LED (Light Emitting Diode) light control.

The invention discloses a method for processing optical fiber I/O (input/ output) out-of-order frames based on field programmable gate array, and relates to a storage technology. The method is characterized by comprising the following steps: building an out-of-order information table entry for storing 'breakpoint' information of a current expected data frame when out-of-order frames occur by utilizing local storage resources in FPGA (field programmable gate array) through finding address/ length list in the system cache when the out-of-order frames occur in the FC (fiber channel) data frame receiving process; inquiring whether the expectation offset equals to the offset in the head part of a receiving frame in the out-of-order information list firstly when the out-of-order frames occur once again; inquiring address/ length list again in the cache if the result can not be found out in the out-of-order list, and finding and calculating the address information corresponding to the out-of-order frames, thus the times of searching for the address/ length list in the cache can be reduced, and the efficiency of data exchanging is improved.

A movement tracking device of human-computer interaction is characterized by comprising a master, a display connected to the master electrically, an identifier tag arranged on a human body, a reader, a two-way communication connector FPGA (field programmable gate array), and a DSP (digital signal processor). The reader reads the position of the human body through the identifier tag, the FPGA is connected to the reader through a signal wire, the DSP is connected to the reader through an I2C/SPI bus, and the DSP is connected to the master through a USB bus in a communicating manner. The movement tracking device is simple, convenient to operate and high in positioning accuracy.

An integrated circuit (10), preferably a field programmable gate array—FPGA or an application specific integrated circuit—ASIC—, comprises a level comparator (30) for comparing a level of a comparator input signal and correspondingly providing a comparator output signal (COS). A sampling unit (40) is coupled to the level comparator (30) for sampling (SAM) the comparator output signal (COS). A bit error test unit (60) receives the sampled comparator output signal (SAM) and determine therefrom an indication of a bit error in a sequence of the sampled comparator output signal (SAM).

The invention discloses an efficient keyword filtering method for FPGA (Field Programmable Gate Array) implementation, and belongs to the technical field of network security. According to the method, a keyword set is preprocessed, rapid matching can be carried out by adopting a method for carrying out hash calculation on keywords and to-be-searched data, the parallel capability of an FPGA is fully utilized, a parallel search engine is realized on the FPGA, rapid keyword search with a certain false alarm rate is carried out, and according to a feedback result searched by the FPGA, the keyword set can be quickly matched with the to-be-searched data. According to the technical scheme, accurate keyword matching searching is carried out without storing keywords on the FPGA, the parallel searching capability of FPGA hardware can be fully utilized, the characteristic that the host and the FPGA are large in off-chip storage capacity can also be utilized, the overall processing performance can reach 40 Gbps or above, and the method has the advantages of being high in searching speed, small in space consumption, free of storing the keywords and the like.

The invention provides a CAN (Controller Area Network) bus communication control system and a communication system, the communication system is based on an SoC (System on Chip) framework consisting ofan MCU (Microprogrammed Control Unit) kernel and an FPGA (Field Programmable Gate Array) kernel which are integrated in the same system on chip, and a CAN bus controller module, an MCU bus mapping module and a CAN bus interrupt signal mapping module are arranged on the basis of logic resources in the FPGA kernel; the CAN bus between the MCU and the off-chip external CAN equipment is integrated inthe chip, the number of the CAN buses can be dynamically configured, and priority classification control of the MCU kernel on each CAN bus controller module is realized, so that the expansibility andusability of the MCU are improved, the design and application complexity of mounting the external CAN equipment by the MCU is reduced, a user can quickly apply the CAN buses, the dependence of the CAN bus priority on the CAN equipment node is reduced, and the controllability of the MCU on the CAN equipment node priority is enhanced. The invention also provides a method for dynamically configuringthe priority of each equipment node of the CAN bus.

The invention belongs to the technical field of Ethernet communication. The invention discloses a method for acquiring, monitoring and analyzing Ethernet signal line speed, which comprises the following steps of: directly hanging a field-programmable gate array on an MII bus between an MAC (Media Access Control) and a PHY (Physical Layer), connecting the field-programmable gate array with a CPU (Central Processing Unit), and the CPU is provided with an Ethernet port, a Consol port and a storage unit of the CPU. According to the invention, the capability of diagnosing the Ethernet equipment iseffectively improved, and the maintenance cost is reduced.

The invention discloses an ATCA (Advanced Telecom Complex Architecture) board card, which comprises a service sub-board and an RTM (Register Transport Module) card sub-board connected with the service sub-board, the service sub-board comprises a CPU (Central Processing Unit) module, a network acceleration module connected with the CPU module, a PCIE (Peripheral Component Interface Express) switching module, a gigabit Ethernet module and a CPLD (Complex Programmable Logic Device) module, and the RTM card sub-board comprises an FPGA (Field Programmable Gate Array) table look-up module, a 10Gbps interface module connected with the FPGA table look-up module and an RTM interface connector. The ATCA board card follows the ATCA standard specification and integrates the service sub-board and the RTM card sub-board, so that the expansibility of the ATCA board card and the RTM card is improved, and the development and maintenance cost of the ATCA is reduced.

The invention discloses a dual-band spectrum data acquisition method, which is applied to the technical field of signal processing. The method comprises the following steps of carrying out analog-to-digital conversion on a to-be-measured analog signal by adopting an analog-to-digital converter in order to obtain a to-be-measured digital signal; carrying out spectral analysis on the to-be-measureddigital signal by using a field-programmable gate array in order to obtain high-band spectrum data in the to-be-measured digital signal; carrying out low-pass filtering on the to-be-measured digital signal by using a finite impulse response filter in order to obtain low-band data in the to-be-measured digital signal; sampling the low-band data according to a preset extraction multiple; and carrying out spectral analysis on the extracted low-band data, and compensating an amplitude spectrum of the extracted low-band data by using an amplitude-frequency response of the finite impulse response filter in order to obtain low-band spectrum data. The invention further discloses a dual-band spectrum data acquisition device, high-band spectrum data and low-band spectrum data can be obtained at thesame time through only one finite impulse response filter and one analog-to-digital converter, and simplicity and reliability are achieved.