Method of fabricating a dual-damascene copper structure
a technology of dual-damascene copper and copper structure, which is applied in the direction of semiconductor/solid-state device manufacturing, basic electric elements, electric apparatus, etc., can solve the problems of current leakage, bad performance of preventing copper atom diffusing, and defects of via plugs, so as to avoid the damage of the semiconductor substrate caused by the precursor of the atomic cvd process, the effect of better step coverage and preferable ability to block copper atoms
Active Publication Date: 2006-11-09
UNITED MICROELECTRONICS CORP
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Benefits of technology
[0011] It is an advantage of the claimed invention that the present invention method comprises forming a substrate-protecting layer on the exposed semiconductor substrate through a PVD process before forming the tantalum nitride layer formed by the atomic CVD process. Therefore the damage of the semiconductor substrate caused by the precursor of the atomic CVD process can be avoided. In addition, the tantalum nitride layer formed by the atomic CVD layer has a better step coverage and a preferable ability to block copper atoms. As a result, the dual-damascene copper structure formed by the present invention method has preferable performance.
Problems solved by technology
However, as the integration of chips increases, the prior-art technology for fabricating the dual-damascene copper structures causes some problems.
Especially when the line width is less than 65 nanometers (nm), the barrier layer formed through the conventional PVD or CVD process has bad step coverage ability and bad conformance, resulting in bad performance of preventing copper atoms from diffusing.
For instance, the titanium nitride layer formed through a conventional PVD process serving as a barrier layer cannot block copper atoms diffusing effectively, and that results in current leakages.
Furthermore, when the conventional barrier layer does not have good conformance, the problem that the barrier layer and copper layer cannot fully fill the dual-damascene hole may occur, which also causes defects of via plugs.
However, when the dual-damascene copper structure is fabricated directly on a silicon substrate, the precursor of the atomic CVD process for forming the tantalum nitride layer causes damage of the silicon substrate or defects of electric devices on the silicon substrate.
In addition, the seed layer of coppers has bad adhesion ability to the tantalum nitride layer formed through the atomic CVD process so as to influence the following processes of forming the copper layer and other devices.
Method used
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Embodiment Construction
[0016] Please refer to FIGS. 2-8. FIGS. 2-8 are schematic views of forming a dual-damascene copper structure according to the present invention, wherein the dual-damascene copper structure of this embodiment is fabricated directly on a semiconductor substrate. First, a semiconductor substrate 40 is provided, wherein the semiconductor substrate 40 is a silicon substrate. The semiconductor substrate 40 has at least a dielectric layer 42 thereon, and FIG. 2 only shows a dielectric layer 42 for clarity. Then, a dual-damascene hole 44 is formed in the dielectric layer 42. As shown in FIG. 2, the bottom of the dual-damascene hole 44 exposes a portion of the semiconductor substrate 40. The surface of the exposed portion of the semiconductor substrate 40 may further comprise a conductive layer 46 composed of silicide or an ion doped region.
[0017] As shown in FIG. 3, a PVD process is next performed to form a substrate-protecting layer 48 on the surfaces of the sidewall of the dual-damascene...
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Abstract
A method for fabricating a dual-damascene copper structure includes providing a semiconductor substrate having a dielectric layer thereon and a dual-damascene hole positioned in the dielectric layer, wherein a portion of the semiconductor substrate is exposed in the dual-damascene hole. A PVD process and an atomic CVD process are sequentially performed to form a substrate-protecting layer and a tantalum nitride layer in the dual-damascene hole. And then a copper layer is formed in the dual-damascene hole.
Description
BACKGROUND OF INVENTION [0001] 1. Field of the Invention [0002] The invention relates to a method of fabricating a dual-damascene copper structure, and more particularly, to a method of fabricating a dual-damascene copper structure through an atomic chemical vapor deposition (CVD) process to form a barrier layer. [0003] 2. Description of the Prior Art [0004] With the increasing complexity of integrated circuits, the multilevel interconnect process has become the typical method used in semiconductor integrated circuit fabrication. To satisfy the requirements for high integration and high speed in integrated circuits (ICs), especially in a deep sub-micro (<0.18 μm) semiconductor process, a copper (Cu) dual damascene process is becoming more widely used as a standard process in forming an interconnection line within the inter-metal dielectric layer of low dielectric constant (low k) materials. Since copper has both a low resistance and a low electromigration resistance, the low k ma...
Claims
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IPC IPC(8): H01L21/4763
CPCH01L21/2855H01L21/28562H01L21/76873H01L21/76846H01L21/76843
Inventor TENG, HSIEN-CHELIN, CHIN-FUCHEN, MENG-CHI
Owner UNITED MICROELECTRONICS CORP
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