39 results about "Clock signal" patented technology

A shift register having individual driving nodes is disclosed. The shift register includes a first clock pull-down module, a second clock pull-down module, a key pull-down module, a self feedback module, and a driving output unit. The first clock pull-down module is used to pull-down the potential of a gate line to a low voltage when the first clock signal is in a high voltage level. The second clock signal pull-down module pulls down the potential of the gate line to the low voltage when the second clock signal is in a high voltage level. The key pull-down module rapidly pulls down the potential of the gate line to the low voltage level after the gate line outputs an output signal. The self feedback module is used to output a driving signal to the key pull-down module. The driving signal output unit outputs a next stage driving signal which is irrelative to the operation of the previous stage shift register.

An improved DDR interface uses single-ended technology and phase-shifts all output data signals and the output source clock signal so that each output signal switches at a different time so that IDDQ spikes caused by I/O switching do not accumulate. A dynamic phase adjustment circuit on the receiver compensates for the phase differences. Clock jitter and skew is reduced and the number of IDDQ pins is reduced to provide a more effective design and high density package.

A clock signal, a data signal, and a latch signal are commonly supplied from a controller to a plurality of the data drivers. The data signal and the latch signal are synchronized with the clock signal. In each of the data drivers, an internal latch signal is generated in synchronization with the clock signal in response to the latch signal. Timing of a rising edge of the internal latch signal is independently controlled in each data driver in accordance with position information where each data driver is arranged.

This invention relates to indoor air quality tester in monitoring field, which is aimed at VOC content as reference, which comprises the following key points: the tester comprises shell, LCD display screen, single machine and matched functional parts, wherein, the shell front side is located with display screen, keys, aim sucking window and its back is located with aim sucking window and battery case. The said single machine and the matched functional parts are connected to the air sensor, humidity sensor, thermal sensor, clock signals, key connection and with its output end connected to LCD display screen and pre-warning device.

A liquid crystal display device is provided which is capable of reducing EMI (ElectraMagnetic Interference) noises while simultaneously responding to requirements for the high-speed transmission of image data, miniaturization and thinning of a signal processing board. A timing controller outputs, in accordance with an input data signal and input clock signal, a data line driving circuit controlling signal, internal data signal, internal clock signal to a data line driving circuit and outputs a scanning line driving circuit controlling signal to a scanning line driving circuit. The timing controller has a clock signal frequency setting mode in which a frequency of each of clock signals is set to a different value and the clock signals are supplied to the data line driving circuits and other data line driving circuits in one region and another region.

This invention describes a method of synchronizing test clocks in an LSSD system to achieve near simultaneous arrival of the clock signals at the inputs of all LSSD registers. The method relies on pipelining the latches to distribute the test clocks, where all pipeline latches are synchronized by the system clock. This enhancement improves the frequency at which the test clocks switch and improve the testing throughput by reducing testing time, resulting in significant reductions in testing hardware and overall time required for system test, without compromising any of the benefits associated with conventional LSSD techniques. The method further enhances the distribution of the test clock signals to points throughout the entire chip, with a distribution network that is tailored according to a desired LBIST speed.

An information processing device includes: a signal receiving portion that receives a signal in which input data that contains first and second bit values different from one another is encoded such that the first bit value is expressed by first amplitude values and the second bit value is expressed by second amplitude values different from the first amplitude values, and such that the same amplitude value does not occur twice in succession and the polarities of the amplitude values are inverted with each cycle; a clock signal extraction portion that extracts a clock signal by detecting polarity inversions in the received signal; a clock signal subtraction portion that subtracts the extracted clock signal from the received signal; and an input data decoding portion that decodes the input data by determining the first and second bit values based on an amplitude value of the signal obtained by subtracting the clock signal.

The pin possesses three output ends A, B and C. An end through a clock signal strobe module is connected to the pin. B end through a high-level strobe module is connected to the pin. C end is leaded out directly from the pin. The said clock signal strobe module is composed of a 4 bits binary counter and a state clamping trigger. The high-level strobe module is composed of 32 frequency dividing circuit and a feedback state control circuit. Based on different signals provided for the pin from external, the multifunctional pin circuit provides different control electrical level for controlling other pins or internal circuits.

A method and system for cycle slip framing is disclosed. The method includes receiving an asynchronous signal and generating a synchronous pulse after receiving the asynchronous signal. The method further provides that the synchronous pulse be used to affect a bit slip that results in the moving of a character frame in the recovered data of a deserializer. According to one embodiment of the invention, the moving of the character frame is prompted by a single control signal of a clock divider circuit which causes the removal of a single clock cycle of a clock signal supplied to said deserializer.

The invention provides a method for outputting high-precision and high-frequency clock signals and an oscillating circuit. The oscillating circuit comprises a low-frequency oscillator, a high-frequency oscillator, a frequency regulator, a first input, a first output and a second output. Fine adjustment configuration signals are input into the low-frequency oscillator through the first input; the low-frequency oscillator outputs low frequency clock signals through the first output; meanwhile, the low frequency clock signals are input into the frequency regulator; the frequency regulator outputs automatic calibrating signals to the high-frequency oscillator through adjustment and compensation of the frequency regulator; finally, the high-frequency oscillator outputs the stable second output, namely high-frequency clock signals. Through the method for outputting the high-precision and high-frequency clock signals and the oscillating circuit, the high-precision and high-frequency clock signals can be output.

An image forming apparatus comprises a plurality of image forming units that respectively form an image, and a plurality of voltage generation circuits that respectively generate voltages for driving the plurality of image forming units. Each of the plurality of voltage generation circuits comprises a voltage generation circuit having a transformer, and generates a voltage by a switching operation that is driven by changing an input voltage of primary side of the transformer, an oscillation circuit that generates a clock signal of a frequency that becomes a reference frequency of the switching operation and a setting unit that sets the frequency of the clock signal that the oscillation circuit generates. The setting units of the plurality of voltage generation circuits set the frequencies of the respective clock signals.

A power-saving circuit for a digital video display device includes a TMDS driving unit converting a TMDS data signal and a TMDS clock signal, a display driving unit driving a display unit based on the horizontal/vertical synchronous signals and the digital video signal input from the TMDS driving unit, a clock signal detecting unit outputting a first or a second level of a clock detecting signal depending on the TMDS clock signal, a controller outputting a first-level of a power-saving signal when the first level clock detecting signal is input, and outputting a second level of power-saving signal when the second level clock detecting signal is input, and a power supply unit supplying a voltage to respective components, and cutting off the supply of the voltage to respective components depending on the level of the power-saving signal or the clock detecting signal.

The invention relates to a nanosecond level pulse peak value detection method and belongs to the technical field of optical communication. According to the method, a nanosecond level pulse signal is broadened through a low-pass filter, then, a clock signal obtained after phase position adjustment is triggered, and therefore an analog-digital converter can sample data more accurately. Under the condition that a high-speed analog-digital converter is not needed, a nanosecond level pulse signal peak value can be detected. With the detection method, the requirement for the sampling rate of an analog-to-digital conversion unit can be lowered, the method is simple and easy to perform, and cost of the needed devices is low.

A light emitting diode controller integrated circuit includes counter circuitry having inputs coupled to a clock signal input pin, a pulse width modulated signal input pin, and a sense input pin, and has a count output coupled to a gate drive signal output to an external power transistor. The power transistor is connected in series between a power lead, a sense resistor, and a light emitting diode. The sense input pin is coupled to the series connection between the resistor and the transistor. The counter circuitry provides a Ton_delay equal to a Toff_delay of the power transistor. By counting up during a Ton_delay and down during a Toff_delay, the controller can be used with power transistors of unknown characteristics.

A system includes a plurality of line cards and a timing card. A clock generation circuit on the timing card generates a clock signal which is pulse width modulated according to information to be transmitted. A clock line supplies the pulse width modulated clock signal to the line cards. The timing card sends a first control word to the plurality of line cards over the clock line after sending a beacon. The first control word includes a size field specifying a first length of first data following the first control word. The timing card sends time of day information over the clock line to the line cards following the first control word. The time of day information may be encrypted. A second control word follows the time of day information. One or more additional control words can follow the second control word before the next beacon.

In a method relating generally to starting a plurality of transmitters (190), a sequence is initiated for each of the plurality of transmitters (190) having corresponding data buffers (121). Latency is set for each of the data buffers (121) responsive to execution of the sequence. The sequence includes: obtaining a read address (108) associated with a read clock signal (106) (501); obtaining a write address (109) associated with a write clock signal (105) (502); determining a difference between the read address (108) and the write address (109) (503); asserting a flag signal (113) associated with the difference (111) (504); and adjusting the read clock signal (106) to change the difference (111) to locate a change of state location for the flag signal (113) to set the latency for a data buffer (121) of the data buffers (121) (505).

A method for arranging a clock-distribution device of an IC is provided. An initial placement of the IC is obtained. The initial placement includes a first portion corresponding to a clock-distribution device, a second portion corresponding to a plurality of modules, and a third portion corresponding to a clock-generation device. The clock-distribution device distributes a plurality of first clock signals to the modules according to a second clock signal from the clock-generation device. The first portion is selected from the initial placement. Clocks within the selected first portion are distributed to obtain a fourth portion of the clock-distribution device. The fourth portion is placed in the initial placement to replace the first portion and to obtain a final placement of the IC. Each module has an input port corresponding to the individual first clock signal, and the clock-generation device has an output port corresponding to the second clock signal.

The embodiment of the invention relates to the technical field of chip design, and provides a chip and a chip power-on starting method, the chip comprises an enabling pin, a clock input pin and a reset pin, and a first clock reset module, a selector and a controller which are arranged in the chip; The input end of the first clock reset module is electrically connected with the clock input pin andthe reset pin, and the output end of the first clock reset module is electrically connected with the selector; And the selector is electrically connected with the enabling pin and a controller of thechip. According to the embodiment of the invention, through simplifying the design of the chip power-on starting, bypassing the power management, high-level security and other complex processing processes related to the power-on starting, the chip power-on starting is realized only by using the clock signal and the reset signal, and the reliability of the chip power-on starting is improved.

A circuit and method provide a charge sharing function during skewed data bus conditions in an integrated circuit memory. The charge sharing circuit includes two additional circuit blocks, one coupled to each of the capacitive lines in the charge-sharing line set, to provide the charge recycling feature. An extra clock signal is active one cycle early during a first clock period to trigger an extra drive circuit to generate a voltage differential on a first capacitive line that is similar to the voltage level generated when real data is being propagated. The presence of an extra voltage signal on the first capacitive line takes place earlier than what would normally happen and allows for proper charge sharing between a second capacitive line and the first capacitive line. Also, there is an additional control signal associated with a last clock period following normal non-skewed charge sharing. The additional control signal triggers a reference read circuit to generate data and a voltage on the first capacitive lines similar to the voltage present during real data for proper charge sharing. The additional read and drive circuit blocks are partial copies of the normal read and drive circuits so that a matching voltage can be generated on the appropriate capacitive signal lines.

The invention discloses a single-stage GOA circuit and a display device, and the circuit comprises a plurality of transistors, wherein the first ends of the plurality of transistors are connected witha preset clock signal, the second ends of the plurality of transistors are connected with a Q point, and the third ends of the plurality of transistors serve as output ends to drive a plurality of rows of scanning lines respectively. According to the invention, the number of GOA units required by the panel assembly is reduced through a mode of driving multiple rows of scanning lines by a single group of GOA units, so the design requirement of a narrow frame is met.

Provided is a multi-mode open-loop type clock extraction apparatus. In the apparatus, a power divider block divides an input data signal into two data signals. A first band-pass filter block and a second band-pass filter block extract a first clock frequency component or a second clock frequency component contained in the data signal output from the power divider. A first amplifier block and a second amplifier block amplify the first clock frequency component and the second clock frequency component respectively. Accordingly, it is possible to extract the respective clock signals corresponding to N data rates from the N data signals with various data rates using a single clock extraction apparatus.

A synchronous clock signal can be adjusted relative to a data signal by decreasing a delay in the synchronous clock signal if a transition of a data signal occurs before a pulse of an offset clock signal which is delayed by one half cycle relative to the synchronous clock signal. The synchronous clock signal can be delayed if the transition of the data signal occurs after the pulse of the offset synchronous clock signal.

The invention relates to a magnetic resonance spectrometer system for realizing clock synchronization of a magnetic resonance spectrometer. The system comprises a clock source module and one or more function modules connected with the clock source module; the clock source module is used for supplying a synchronous clock signal to each function module; and each function module comprises a work clock synchronization sub-module which is used for receiving a synchronous clock signal corresponding to the function module and acquiring one or more work clock signals which are synchronous with the clock source module and have low clock jitter based on the synchronous clock signal. The invention provides a package of solutions for the whole clock synchronization for the spectrometer system, the clock synchronization among the constituent units of the spectrometer system is realized, and the requirement that the constituent units of the spectrometer acquire the clock which is synchronous with the clock signal of the spectrometer clock source unit and has low jitter is met, so that a solid foundation is laid for a spectrometer system to serve magnetic resonance high-quality scanning imaging.

A memory device includes a memory array and a frequency-to-voltage converter. The memory array includes a plurality of memory cells arranged in rows and columns, and gates of the memory cells in the same row are coupled to each other and connected to a word line. The frequency-to-voltage converter coupled between the word line and a clock signal source outside the memory device receives a clock signal, and correspondingly outputs different voltages to the word line in accordance with the frequency of the clock signal.

The present invention provides an arrangement and method for a galvanically insulated, AC/DC sensitive differential current measurement. The arrangement is an electric circuit arrangement having a high resolution having: a toroid current transformer having at least one secondary winding for detecting a differential current; a driver circuit for powering the secondary winding; a first oscillator circuit for controlling the driver circuit and for generating a time-modulated binary oscillator signal having dwell times in a state 1 and a state 2; a second oscillator circuit for determining the corresponding dwell time in the states 1 and 2 in high resolution by means of a clock signal having a clock rate independent of the oscillator signal; an evaluation device for evaluating the dwell time; and a data interface for outputting a differential-current measuring value; the driver circuit and the second oscillator circuit each being realized as structurally individual, integrated circuits.

Frequency synthesizer circuitry employs a delay line. A reference clock signal propagates through successive stages of the delay line, and the currents drawn by output buffers of all of the stages are added at a common node. The common node current is converted to a voltage, which is AC-coupled to an output buffer ring oscillator of the frequency synthesizer. The output buffer ring oscillator includes a plurality of inverters connected in a series. A feedback connection including a resistor is provided from an output node of the last inverter to an input node of the first inverter.

The invention discloses a clock frequency acquiring system and a clock frequency acquiring method. The clock frequency acquiring method includes A, connecting a tested clock signal source into the clock frequency acquiring system; B, sequentially generating clock signals of various frequencies from small to big by the clock frequency acquiring system, and judging whether the clock signals of various frequencies can be divided exactly by the tested clock signal source or not; C, when the clock signals of various frequencies can be divided exactly by the tested clock signal source, storing the clock signals, and calculating frequency of the tested clock frequency according to stored clock signals. By the system and the method, acquiring of frequency of high-frequency clock signals through low-frequency clock signals is realized without being influenced by factors like hardware conditions and cost.