Method and apparatus for adjustment of synchronous clock signals

[0014] Illustrative embodiments of the present invention are described with reference to data signals, synchronous clock signals and offset clock signals. Timing diagrams showing the relative timing of a data signal, a synchronous clock signal and offset clock signal are presented in FIGS. 1-3. Referring to FIG. 1, a synchronous clock signal 10 includes a train of synchronous clock pulses 12 that can have a period 14 corresponding to a data cycle 16 of a data signal 18. An offset clock signal 20 includes a train of offset clock pulses 22 that have the same period 14 as the synchronous clock signal but are offset from the synchronous clock pulses 12 by one half period (e.g., one half of data cycle 16). The signals shown in FIG. 1 represent ideal timing wherein the synchronous clock pulses 12 should occur at the center of each data cycle 16 (e.g., at time A). In the ideal representation shown in FIG. 1, any transition of the data signal 18 should occur simultaneously with an offset clock