31 results about "Data signal" patented technology

A drive circuit is provided for an OLED pixel display. The drive circuit is adapted for use with a reference voltage source. It includes a first transistor and an OLED. The output circuit of the first transistor is operably connected between the reference voltage source and the OLED. Transmission gate means responsive to a control signal are provided to transmit a data signal to the first transistor. Means are provided for controlling the first transistor in accordance with a time domain modulation signal to provide an average current to the OLED which is a function of the data signal.

The invention discloses a pixel circuit, a driving method of the pixel circuit, a display panel, and a driving method of the display panel. The pixel circuit comprises a first transistor, a drive transistor, a second transistor, a threshold value compensation module, a first capacitor, a second capacitor, a light-emitting element and a fifth transistor, wherein the first transistor is used for transmitting a signal of a data signal end to a first node by responding to an enable signal of a scanning signal end; the threshold value compensation module is used for transmitting the signal of the first node to a second node through the drive transistor by responding to an enable signal of a second on-off control signal end; a first pole plate of the first capacitor is electrically connected tothe first node. For the pixel circuit provided by the invention, the data writing stage is carried out first, the initialization stage, the compensation stage and the light emitting stage are then carried out, the time of the compensation stage of the pixel circuit can be increased, and the compensation effect is promoted.

An organic light emitting diode pixel driving circuit includes a pixel capacitor for storing a received voltage and coupling a change valve of the voltage at a first electrode thereof to a second electrode thereof; a first transistor for providing a reference voltage to the first electrode of the pixel capacitor under the control of a first light emitting signal; a third transistor for transmitting a data voltage to second electrode of the pixel capacitor under the control of the first scanning signal; and a fourth transistor; thereby overcoming the uneven display of the entire image, which is caused by the drift of the threshold voltage of the driving transistor and the different driving current driving the different OLEDs to emit light when the different OLEDs receive the same image data signal, the different driving current is caused by the difference the high-level power supply voltages.

Disclosed is an output buffer circuit including a first differential transistor pair for differentially receiving a data signal from a differential input pair; and a second differential transistor pair for differentially receiving an emphasis data signal from another differential input pair; a pair of output resistor circuits via which the drains of first and second differential transistor pairs are connected to a power supply, said output resistor circuits each including a transistor; and a logic circuit adapted for receiving the data signal and the emphasis signal and for supplying a control signal which is of first and second values at the time of preemphasis and at other times to the transistors of the output resistor circuit, wherein the output resistance is relatively made larger at the time of emphasis, while being relatively smaller at the time of deemphasis.

An LCD device having dual source drivers and related driving method are disclosed for performing data signal driving operation by making use of a data writing synchronous control mechanism. The operation of the data writing synchronous control mechanism includes furnishing all image data signals to both the first and second source drivers, latching odd and even image data signals by the first and second source drivers respectively, performing a signal processing process on the odd image data signals for generating a first set of analog data signals by the first source driver, performing a signal processing process on the even image data signals for generating a second set of analog data signals by the second source driver, writing the first set of analog data signals into a plurality of first pixel units, and writing the second set of analog data signals into a plurality of second pixel units.

A liquid crystal display device is provided which is capable of reducing EMI (ElectraMagnetic Interference) noises while simultaneously responding to requirements for the high-speed transmission of image data, miniaturization and thinning of a signal processing board. A timing controller outputs, in accordance with an input data signal and input clock signal, a data line driving circuit controlling signal, internal data signal, internal clock signal to a data line driving circuit and outputs a scanning line driving circuit controlling signal to a scanning line driving circuit. The timing controller has a clock signal frequency setting mode in which a frequency of each of clock signals is set to a different value and the clock signals are supplied to the data line driving circuits and other data line driving circuits in one region and another region.

The invention discloses a display panel and a multiplexing drive circuit for driving the display panel. The multiplexing drive circuit comprises a plurality of drive units, wherein each drive unit receives eight channels of data signals with negative-positive-positive-negative-positive-negative-negative-positive polarity or negative-positive-negative-positive-positive-negative-positive-negative polarity so as to enable twenty-four data lines to sequentially receive the data signals with the positive-negative-negative-positive-negative-positive-positive-negative positive polarity or the negative-positive-negative-positive-positive-negative-positive-negative polarity; therefore, when the display panel displays pure color images, any two adjacent sub-pixels of the same color in any row of sub-pixels respectively receive the data signals with different polarities, and the problem of picture crosstalk caused by the same color along the row direction is further improved; furthermore, the multiplexing drive circuit is less in winding, so that the thickness of the display panel can be reduced.

The invention discloses a driving circuit of a silica-based micro displayer. The driving circuit comprises a pixel array circuit composed of pixel circuits distributed in an array, a column driving circuit, a row driving circuit and a control circuit. The pixel circuits are used for storing data signals connected to a circuit column line of a pixel array and generating micro current or micro voltage when selection signals connected to a pixel array circuit row line are valid and accordingly driving micro luminescent devices connected to the pixel circuits. The column driving circuit comprisesa column location selection circuit, a column level switching circuit and a sampling maintenance circuit. The row driving circuit comprises a row location selection circuit and a row column level switching circuit. The control circuit comprises a time schedule controller and a digital-to-analogue converter. According to the driving circuit, by adopting a pixel circuit access mode with multiple voltage domains and higher signal driving capacity, the flexibility and adaptability of the micro displayer are improved, optimal design on the driving circuit is conducted through an extension mode, anda more flexible data shift mode with higher display resolution is supported.

A power-saving circuit for a digital video display device includes a TMDS driving unit converting a TMDS data signal and a TMDS clock signal, a display driving unit driving a display unit based on the horizontal/vertical synchronous signals and the digital video signal input from the TMDS driving unit, a clock signal detecting unit outputting a first or a second level of a clock detecting signal depending on the TMDS clock signal, a controller outputting a first-level of a power-saving signal when the first level clock detecting signal is input, and outputting a second level of power-saving signal when the second level clock detecting signal is input, and a power supply unit supplying a voltage to respective components, and cutting off the supply of the voltage to respective components depending on the level of the power-saving signal or the clock detecting signal.

The invention discloses a Baudrate evaluation IP core system applied to a serial bus analyzer, and relates to the field of serial bus Baudrate evaluation of a tester system. The system aims at solving the problems that the existing Baudrate evaluation method is low in accuracy, reliability and precision when obtaining the Baudrate. According to the system, the serial bus data signal output end of an AX18-bit memory mapping slave port S8 is connected with the serial bus data signal input end of a data input cache FIFO module; the serial bus data signal output end of the data input cache FIFO module is connected with the serial bus data signal input end of a Baudrate evaluation algorithm core control module; the serial bus data signal output end of the Baudrate evaluation algorithm core control module is connected with the serial bus data signal input end of a data output cache FIFO module; and the data signal output end of the data output cache FIFO module is connected with the data signal input end of the AX18-bit memory mapping slave port S8. The system is used for obtaining the Baudrate.

A display control device receives an image signal, and is connected to a display panel to display the image signal in a matching manner and electrically connected to a USB (universal serial bus) device, wherein the display control device comprises a display controller, a power controller and a USB transmission module; the display controller and the power controller are mutually electrically connected; the USB transmission module is electrically connected to the display controller, the power controller and the USB device, and obtains and provides a USB data signal generated by the USB device to the display controller or the power controller; the USB data signal is loaded with a shutdown instruction or a startup instruction; when the USB transmission module receives the shutdown instruction, the shutdown instruction is transmitted to the display controller; the display controller informs the power controller to control the USB data signal; the display controller comes into a standby power supply state; when the USB transmission module receives the startup instruction, the startup instruction is transmitted to the power controller, and the power controller awakens the display controller and informs the display controller to control the USB data signal.

The employment of cascoding in connection with improving mixer isolation in a Gilbert mixer circuit. In this vein, there is broadly contemplated herein, inter alia, the provision of a mixer suitable for use in a direct-conversion radio receiver operating in the 57-64 GHz industrial, scientific, and medical (ISM) band. Such a receiver may be integrated along with a transmitter entirely on a silicon integrated circuit and can be used to receive and transmit data signals in such applications as wireless personal-area networks (WPANs). Numerous other applications, of course, are available for a mixer with improved LO-to-RF isolation, particularly at millimeter-wave frequencies where high LO-to-RF isolation is difficult to achieve.

A semiconductor device includes a pre-buffer for transferring a data signal on the basis of a first power supply voltage, a main buffer for amplifying and outputting the data signal transferred by the pre-buffer on the basis of a second power supply voltage different from the first power supply voltage, a switch unit for controlling a conductive state between the pre-buffer and the main buffer on the basis of a switch control signal, and a control circuit for generating the switch control signal for controlling the pre-buffer to set an output level of the pre-buffer to ground potential in accordance with transition of logical level of the switch control signal.

The invention relates to the technical field of LED control, and particularly discloses an LED control system which comprises a controller and an LED lamp string electrically connected with the controller, wherein the controller comprises a first data output port and a second data output port and is used for sending out a first data signal through the first data output port and sending out a second data signal through the second data output port, and the first data signal and the second data signal are opposite in phase; and the LED lamp string can receive the first data signal and the second data signal through a data receiving port, can realize display control of the LED lamp according to the first data signal and the second data signal, and can perform power supply conversion on the first data signal and the second data signal to realize power supply of the LED lamp. The LED control system provided by the invention is simple in implementation mode, low in cost and high in reliability.

Provided is a multi-mode open-loop type clock extraction apparatus. In the apparatus, a power divider block divides an input data signal into two data signals. A first band-pass filter block and a second band-pass filter block extract a first clock frequency component or a second clock frequency component contained in the data signal output from the power divider. A first amplifier block and a second amplifier block amplify the first clock frequency component and the second clock frequency component respectively. Accordingly, it is possible to extract the respective clock signals corresponding to N data rates from the N data signals with various data rates using a single clock extraction apparatus.

A synchronous clock signal can be adjusted relative to a data signal by decreasing a delay in the synchronous clock signal if a transition of a data signal occurs before a pulse of an offset clock signal which is delayed by one half cycle relative to the synchronous clock signal. The synchronous clock signal can be delayed if the transition of the data signal occurs after the pulse of the offset synchronous clock signal.

A server system includes an expander unit and a baseboard management controller (BMC). The expander unit is electrically connected to a hard-disk unit, and configured to transmit a command signal to the hard-disk unit to read hard-disk information of the hard-disk unit. The baseboard management controller (BMC) is electrically connected to the expander unit, and configured to store the hard-disk information. After the hard-disk unit receives the command signal, the hard-disk unit generates a data signal according to the command signal and a state of the hard-disk unit, and transmits the data signal to the expander unit, so as to generate the hard-disk information according to the data signal.

The present invention discloses an information receiver and an information controller, wherein the information receiver includes a power supply circuit, a characteristics information receiver of which includes a singlechip, a data receiving part, and an infrared ray transmission part, a data signal output end of the data receiving part is connected to the singlechip, a data signal input end of the infrared ray transmission part is connected to the singlechip, and the data receiving part employs a radio receiving set or an infrared ray receiving set. The information controller includes the information receiver, a signal output circuit, a liquid crystal display, a keyboard, and a data memory, wherein the signal output circuit, the liquid crystal display, the keyboard and the data memory are connected to the singlechip separately, an information memory is provided with a data transmission device, a data receiving device and a singlechip. The information receiver and the information controller of the invention are telecommunicated with the information memory, which may be used for a long distance recognition of vehicle identification in a car park.

The invention provides a display panel and a display device, and belongs to the technical field of display. In the display panel, each of a first pixel circuit located in a first display area and a second pixel circuit located in a second display area comprises a driving circuit with two grid electrodes, and one grid electrode is used for receiving a power supply signal. The potential of the power supply signal received by the grid electrode of the driving circuit in the first pixel circuit is different from that of the power supply signal received by the grid electrode of the driving circuit in the second pixel circuit. Therefore, the independent control of the characteristics of the transistor included in the driving circuit in the first pixel circuit and the characteristics of the transistor included in the driving circuit in the second pixel circuit is realized. Therefore, in different scenes of the first pixel circuit and the second pixel circuit, the source driving circuit transmits data signals with small potential difference to the two pixel circuits, so that two light-emitting elements driven by the two pixel circuits have the same light-emitting brightness. Correspondingly, the working power consumption of the source electrode driving circuit is low.

The invention relates to a building energy consumption monitoring and management system which comprises a plurality of lighting areas, a plurality of lighting lamps arranged in each lighting area anda pedestrian volume data collector, and further comprises a control module. The control module comprises a time control module, a control unit and a display. The control unit is electrically connectedwith the lighting lamp in the lighting area. The invention further relates to a monitoring method, a building energy consumption monitoring management system is included, a remote background is further included, the control module further comprises a wireless signal transmission module, and the wireless signal transmission module is electrically connected with the control unit. And the control module is used for processing the data signals acquired by the pedestrian volume data acquisition device and comparing the data signals with the data signals acquired by the light acquisition device soas to adjust the brightness in the building. By means of the control module, energy consumption can be saved to the maximum extent, and convenience and practicability are achieved.

The invention discloses a three-dimensional measurement method and device for a net mouth shape of a fishing trawl net in a marine fishery industry, relates to the field of trawl net fishing of the marine fishery industry, and solves the shortcoming that the fishing efficiency is influenced caused by the fact that the whole net mouth shape cannot be acquired in the conventional trawl net mouth measurement. According to the key points of the technical scheme, the measurement device comprises a plurality of positioning array elements which are uniformly arranged at intervals and positioned on atrawl net mouth, a master control machine for controlling the positioning array elements and receiving the position information detected at specified points, and a data transmission cable for transmitting data signals between the master control machine and each positioning array element; and the master control machine obtains the position information of each positioning array element, and determines the net mouth shape of the trawl net according to the relative position of the respective positioning array elements. By virtue of the three-dimensional measurement method and device for the net mouth shape of fishing trawl net in the marine fishery industry, the accurate three-dimensional shape of the net mouth of the trawl net can be accurately determined, the net mouth can be adjusted conveniently and the trawl net fishing efficiency can be improved.

The invention discloses an active noise control window for target tracking. The window comprises a metal window frame structure and an active noise control system. The metal window frame structure is formed by combining a metal round pipe (4) and a metal square pipe (5), a motor (11) is installed at the top end of the metal round pipe (4), the motor (11) rotates to drive a metal wafer (12) to rotate, the metal wafer (12) and the metal round pipe (4) are welded and fixed, and the motor (11) rotates to drive the metal round pipe (4) to rotate leftwards and rightwards to any angle. The active noise control system comprises a plurality of reference microphones (8), a plurality of secondary loudspeakers (9), a plurality of physical error microphones (7), a camera (3), a motor driver and a controller (6), and an input port of the controller is connected with data signal lines of the reference microphones (8), the physical error microphones (7) and the camera (3). An output port is connected with data signal lines of the secondary loudspeakers (9) and the motor driver. The invention further discloses a corresponding control method.

The invention provides a portable system for reading and writing a PCMCIA memory card. The portable system comprises a PC card adapter board (1), a transmission cable (2), a PC card driver (3) and a PCMCIA memory card interface, wherein the PC card adapter board (1), the transmission cable (2), the PC card driver (3) and the PCMCIA memory card interface are connected to a computer ISA bus; the PC card adapter board (1) is provided with a driving chip for driving signals, and the PC card driver (3) is provided with a filter circuit and a PC card slot control chip; an address signal line and a control signal line of the ISA bus are connected to a PC card slot control chip through a driving chip of the PC card adapter board (1), the matching resistor (4), the transmission cable (2) and a filter circuit of the PC card driver (3) in sequence; a data signal line of the ISA bus is connected to the PC card slot control chip through a matched resistor (4); and the PC card slot control chip is used for converting the ATA interface of the PCMCIA card into a bus signal. According to the invention, the reliability of long-distance reading and writing of the PCMCIA memory card by the computer is improved.

Devices and methods for digital to analogue conversion (DAC) are provided, in which the analogue outputs of an even number of digital to analogue converters are combined. The individual converters operate on the same data but there is a relative time delay between the input digital signal received by one or more of the converters and the input digital signal received by other of the converters, wherein the delay is a fraction of the data sample period. Moreover, the data signal fed to half of the converters has an inverse relationship with the data signal fed to the other half of the converters and their analogue outputs are subtracted. Dither and filtering techniques may also be employed.

The invention discloses a high-reliability plug-in type light-emitting diode with a built-in driving IC, and belongs to the field of diodes, the high-reliability plug-in type light-emitting diode with the built-in driving IC comprises a built-in IC control chip, a lead frame and a light-emitting chip, the lead frame comprises five functional welding pins, and the five welding pins are respectively DO, Gnd, Vcc, DI1 and DI2. The DO contains DO1 and DO2; the built-in IC control chip is used for processing data signals of the controller and a superior pixel point; the light-emitting chip is used for radiating visible light; the DO is used for outputting a data signal; and the Gnd and the Vcc are respectively a positive electrode and a negative electrode. Normal operation of the pixel points is guaranteed, meanwhile, double-path signal transmission is adopted, operation of the secondary pixel points is not affected after a single pixel point is damaged, normal display of the whole color is guaranteed, the use reliability is higher, the market use requirement is met, the maintenance probability is reduced, and the high-reliability plug-in type light-emitting diode is suitable for application and popularization.

The invention discloses a device for improving the test rate of a DDR device, and the device is characterized in that the device comprises a software unit, a hardware unit, and a switching circuit; the software unit is used for defining a plurality of driving edge characteristics according to a system signal, doubling the clock frequencies of a first to-be-written control signal, a data signal andan address signal to obtain a second to-be-written control signal, the data signal and the address signal, and inputting the second to-be-written control signal, the data signal and the address signal into the hardware unit; the hardware unit is used for doubling the clock frequency of the second to-be-written control signal, the data signal and the address signal to obtain a third to-be-writtencontrol signal, the data signal and the address signal, and inputting the third to-be-written control signal, the data signal and the address signal into the switching circuit; the switching circuit is used for writing the third to-be-written control signal, the data signal and the address signal into a DDR device; and the DDR device response data signal is output to a test system through the switching circuit.