Digital to analogue conversion

[0081]FIG. 12 illustrates an alternative enhancement of this embodiment 120 in which high rate dither at 2×Fs 126 is shaped by filter 128. Filtered dither is generated at 2×Fs and a switch 120 directs the even samples towards DAC1123a and the odd samples towards DAC2123b. An advance operation 129 corresponds to applying the odd sample values to the even sample instants to match to the sample instants of the LPCM input 121. The semi-sample delay operation 122b corresponds to DAC2123b being clocked on the opposite clock phase to DAC1123a. The input to DAC2123b is inverted by inverter 125, and the analogue outputs of the two DACs are combined are combined subtractively 124 to produce the final analogue output signal.

[0082]In general, this embodiment features a dither stream generated at a higher rate than the sample rate of the input digital signal (hi-rate dither), typically at the reconstruction rate of the output analogue signal, where samples from the dither stream are sequentially di

[0087]FIG. 13 shows a further development of this embodiment 130, in which dither 136 is initially generated at 1×Fs. It is then passed through filter 138a for application to DAC1133a and through filter 138b for application to DAC2133b. The input to DAC2133b is inverted by inverter 135 and delayed by a time delay 132b. The analogue outputs of the two DACs are combined subtractively 134 to produce the final analogue output signal.

[0088]This operation is actually equivalent to the operation in FIG. 12, where the 2×Fs dither generator 126 operates by upsampling the 1× dither generator 136 by interspersing zeros between the sample values. Filter 138a comprises the even taps of the impulse response of filter 128 and filter 138b comprises the odd taps. It is shown as a separate diagram since the arrangement looks quite different despite the underlying close connection. Nevertheless it fits the description of hi-rate dither above.

[0089]Design of filters 138a and 138b can thus be performed by